AI Accelerator Architect for Energy-Efficient LLM Silicon

Normal Computing Corp.; Mountain View (CA); On-site; USD 260,000 - 420,000; Full time

Job summary

Normal Computing is seeking a Hardware ASIC Architect to define silicon and system microarchitecture for a novel AI accelerator platform, targeting large energy efficiency gains for LLM and diffusion model inference. You will lead co-design across hardware and software teams to translate research into tangible hardware blocks.

Join a collaborative, research-driven environment in Mountain View, with ambitious goals and close coupling to compiler, RTL, and analog teams.

Qualifications

• Degree in Electrical Engineering, Computer Engineering, or related field; PhD welcome but not required.
• Extensive experience in architecture or microarchitecture of AI accelerators or high-performance digital systems.
• Ability to translate workload analysis to datapath widths, pipeline stages, and area/power estimates.
• Experience with simulation-driven architecture and cycle-accurate models.
• Familiarity with quantization and reduced-precision inference.
• Experience writing microarchitecture specifications and working with RTL engineers.
• Proficiency in Python or C++ and familiarity with SystemVerilog or RTL.
• Comfort in discovery-driven architecture research.

Responsibilities

• Define architecture and microarchitecture for AI accelerator compute blocks (PE array and datapath).
• Translate workload analyses into hardware specifications for RTL implementation.
• Defend PPA tradeoffs across the stack from algorithm to physical design.
• Partner with compiler on ISA co-design; align programming model with microarchitecture.
• Prototype pre-silicon validation with FPGA design teams to de-risk tapeout.
• Stay current with AI accelerator research and articulate differentiators.

Skills

Architecture design

Microarchitecture

Python / C++

SystemVerilog

Education

Bachelors in Electrical/Computer Engineering

PhD welcome but not required

Tools

RTL design

RTL simulators

Job description

Normal Computing is seeking a Hardware ASIC Architect to define silicon and system microarchitecture for a novel AI accelerator platform, targeting large energy efficiency gains for LLM and diffusion model inference. You will lead co-design across hardware and software teams to translate research into tangible hardware blocks.

Join a collaborative, research-driven environment in Mountain View, with ambitious goals and close coupling to compiler, RTL, and analog teams.