Lead ASIC Architect for Energy-Efficient AI Accelerators

Normalcomputing; Mountain View (CA); On-site; USD 180,000 - 320,000; Full time

Job summary

Normal Computing is seeking an Hardware ASIC Architect to define silicon and system microarchitecture for a novel AI accelerator platform. You will drive co-design between hardware and software, translating transformer workloads and diffusion execution flows into custom compute tiles and interconnects for high efficiency.

Lead pre-silicon validation planning, work with FPGA and RTL teams, and stay current with AI accelerator research to differentiate Normal's approach.

Qualifications

• Degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent.
• Experience in architecture or microarchitecture of high-performance digital systems, AI accelerators, or similar compute engines.
• Fluency moving between algorithm-level analysis and hardware specifications.

Responsibilities

• Define architecture and microarchitecture of AI accelerator compute blocks.
• Translate workloads into hardware specifications with clear microarchitecture docs for RTL.
• Evaluate full-stack PPA tradeoffs and defend decisions across layers.
• Collaborate on ISA co-design with compiler teams and ensure alignment.

Skills

PE array design

Datapath design

Sparsity exploitation

Reduced-precision compute

ISA co-design

Education

Bachelor's in EE/CE/CS

Tools

SystemVerilog

RTL

Job description

Normal Computing is seeking an Hardware ASIC Architect to define silicon and system microarchitecture for a novel AI accelerator platform. You will drive co-design between hardware and software, translating transformer workloads and diffusion execution flows into custom compute tiles and interconnects for high efficiency.

Lead pre-silicon validation planning, work with FPGA and RTL teams, and stay current with AI accelerator research to differentiate Normal's approach.