Accelerator RTL Design Engineer - Remote-Friendly Equity

HushOne, Inc.; Kirkland (WA); Vor Ort; USD 120.000 - 180.000; Vollzeit

Benefits dieser Stelle

Stock options

401(k) with company match

Health, dental and vision coverage

Gym membership

AI tokens budget

Referral bonuses

Zusammenfassung

HushOne, Inc. is building hardware accelerators and subsystems with a focus on correct digital logic and fast, verifiable RTL.

You will create synthesizable SystemVerilog RTL, manage interfaces, and drive power-aware behavior from concept through verification and integration. The role emphasizes design for verifiability, timing, and backpressure awareness, with collaboration across verification, compiler, and physical design teams from day one.

Qualifikationen

• Strong SystemVerilog/RTL fundamentals and experience.
• Clear understanding of pipelines, resets, clock domains and backpressure.
• Design for verifiability, not handoff to downstream teams.
• Have taped out or advanced a design to a comparable commitment point.

Aufgaben

• Develop synthesizable RTL and interfaces for accelerators or subsystems.
• Collaborate with verification, compiler and physical-design engineers from the start.
• Track area, frequency and energy against workload and avoid optimizing non-representative benchmarks.

Kenntnisse

SystemVerilog RTL

Pipelines

Clock Domains

Backpressure

Verifiability by design

Tape-out experience

Jobbeschreibung

HushOne, Inc. is building hardware accelerators and subsystems with a focus on correct digital logic and fast, verifiable RTL.

You will create synthesizable SystemVerilog RTL, manage interfaces, and drive power-aware behavior from concept through verification and integration. The role emphasizes design for verifiability, timing, and backpressure awareness, with collaboration across verification, compiler, and physical design teams from day one.