Staff Layout Engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED is seeking a layout engineer for its Library Group. The role focuses on memory, I/O, and standard cells with strong Cadence tool experience and submicron process knowledge. Lead junior engineers and drive layout methodology improvements.

Responsibilities include strict adherence to layout guidelines, floor-planning, and timely delivery of verified layouts across CMOS processes from 16nm down to 2nm and beyond.

Qualifications

• Minimum 8 years of layout experience.
• Experience in memory, I/O, and standard cell layout.

Responsibilities

• Understand and apply all layout guidelines and rules for quality layout.
• Schedule time-lines and layout floor-planning.
• Deliver high-quality layout and verification with minimal supervision.

Skills

Memory layout design

Physical verifications

LVS

DRC

ERC

Antenna

Electro Migration

Floor-planning

Hierarchy layout

Chip integration

Memory compiler

Script programming

SKILL programming

Team leadership

Technology reviews

Independent work

Tools

Cadence Virtuoso XL/VXL/EXL

CALIBRE verification tools

Job description

The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.

In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.

Requirements:

• Strong layout knowledge with a minimum of 8 years of experience
• Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
• Strong layout knowledge in submicron processes, e.g. 16nm, 7nm, 5nm,2nm ,A14 and below
• Experienced in digital (standard cell, memory, I/O) layout
• Experienced in analog layout is also a plus

Job description:

• Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
  Schedule time-line & layout floor-planning
• Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
• Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem)

• Strong experience in memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes.

• Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.

• Good experience in Floor-planning, hierarchy layout and chip integration.

• Experience in memory compiler will be a plus.

• Knowledge of Script Programming and SKILL Programming would be a plus.

• Able to leador train a team of junior engineers

• Good knowledge of memory layout topology.

• Ability to lead new technology reviews to compile documentation of layout methodology, layout flow and guidelines.

• Self-reliant, with the ability to work independently as well as in a team.

• Good leadership quality in project management.