[2027 Campus Hire] Full Custom Layout Engineer

MediaTek Research Lab Inc.; Singapore; On-site; SGD 42,000 - 72,000; Full time

Job summary

MediaTek’s Layout team is seeking a Full Custom Layout Engineer as part of our 2027 campus hire program in Singapore. You will contribute to high-quality IC layouts for our cutting-edge chips in a fast-paced environment.

Fresh graduates with strong learning drive are welcome. You will master floorplanning, power mesh planning, and top-down integration while collaborating with cross-site teams to meet tape-out milestones.

Qualifications

• Bachelor’s degree in Electrical/Electronic Engineering.
• Transistor level knowledge for circuits and device layout.
• Understanding analog layout fundamentals (floorplan, matching, EM and IR).
• Team player with cross-team communication and time management.
• Proficiency in scripting (Tcl, Perl or C-shell) is a plus.

Responsibilities

• Implement high-quality layout meeting designer specs and milestones.
• Diligently perform DRC/LVS/ERC verifications on layout designs.
• Optimize layout for power, performance, area and schedule.
• Collaborate with multi-functional teams across sites to improve layout.
• Develop in-house IP/library as needed.

Skills

Floorplanning

Power mesh planning

Block placement

Signal routing

DRC/LVS debugging

Layout editors

Scripting Tcl/Perl/C-shell

Education

Bachelor’s degree in Electrical/Electronic Engineering

Job description

[2027 Campus Hire] Full Custom Layout Engineer

Category

Chip Design

Location

Singapore

Experience

No Work Expe.

Job Description

MediaTek’s Layout team is responsible to implement top quality layout of the integrated circuit for our chips. We are looking for result-driven candidates who can thrive under a fast-pace working environment and possess a strong desire to create an impact in the organization.Fresh graduates who are eager to get involved with industry most advanced semiconductor process technology are a perfect fit for our team. Candidates with strong passion in learning, problem solving, and decision-making skills are welcome to apply.

Candidates will be able to develop in the following area:

• Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing, matching and top-down integration flow
• Proficient in Synopsys/Cadence layout editor and physical verification tools; analytical and skillful in debugging DRC/LVS and all other verifications[What you will do]
• Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and fast paced milestones
• Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow
• Work closely and communicate effectively with multi-functional teams and multi-site to constantly optimize layout for better power, performance, area and schedule
• Responsible for in-house IP/library developments#LI-WC1

Main Requirements and Qualifications

• [Are you the right talent?]
• - Bachelor’s degree in Electrical/Electronic Engineering
• - Has transistor level knowledge for circuits and device layout structure
• - Understands analog layout fundamentals, such as floorplan, device matching, EM and IR
• - Have a good grasp of DRM of advanced node CMOS technologies
• - Team player and effective in cross-team communication and time management
• - Proficiency in script programming (e.g. Tcl, Perl or C-shell) is a plus