Senior Integrated Circuit Designer - Layout

ASTERA LABS SINGAPORE PRIVATE LIMITED; Singapore; On-site; SGD 90,000 - 120,000; Full time

Job summary

ASTERA LABS SINGAPORE PRIVATE LIMITED seeks a motivated Integrated Circuit Designer to collaborate with layout and design engineers across multiple time zones. You will design and develop IC layouts for advanced CMOS nodes, focusing on minimizing parasitics and meeting tight DRC/LVS constraints.

Your role includes managing manufacturing processes, developing test procedures, and advising on process technology while maintaining equipment.

Qualifications

• Bachelor’s degree in electrical engineering is required.
• 2+ years of experience in layouts for high-speed analog IC designs in finFET technology.
• Experience with layout extraction tools and analyzing layout parasitics to achieve high-quality layout for high-speed circuits.
• EMIR and antenna DRC rules aware layout practices.
• Experience writing SKILL and TCL scripts is recommended.

Responsibilities

• Design and develop the layout for ICs using floor planning and building blocks.
• Manage manufacturing process including technology yield and performance.
• Develop test programmes and procedures to ensure product performance.
• Advise on semiconductor process technology and maintain/repair process equipment.

Skills

Layout design

Floor planning

Parasitic minimization

EMIR/antenna DRC rules

TCL scripting

High-speed analog IC design

Team collaboration

Education

Bachelor’s degree in Electrical Engineering

Tools

Layout extraction tools

TCL scripting

Job description

The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones

As an Integrated Circuit Designer, you will be part of a key team designing and developing sophisticated advanced node CMOS products.

Key Job Duties:

• The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [floor planning, creating layouts of building blocks and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS]
• The management of manufacturing process of the products, including technology yield and performance of the products.
• The development of test programmes and procedures to ensure the products meet their performance specifications.
• The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment.

Basic Qualifications:

• At least a bachelor’s degree in electrical engineering

Required Experience:

• 2+ years of experience in the development of layouts for highspeed analog IC designs in finFET technology.
• Experience with layout extraction tools and to analyzing layout parasitic to achieve high quality layout for highspeed circuits.
• EMIR and antenna DRC rules aware layout practices.
• Experience writing SKILL and TCL scripts is highly recommended