Staff Layout Engineer

Broadcom; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom is seeking a Staff Layout Engineer in Singapore to design memory, I/O, and standard cells. You will lead layout efforts with strong knowledge of submicron processes (16nm/7nm/5nm/2nm and below) and utilization of Cadence tools, CALIBRE and Hercules. Relocation to Singapore is required.

The role emphasizes independent work, teamwork, and potential to mentor junior engineers within the Library Group, part of Central Engineering.

Qualifications

• Minimum 8 years of IC Layout experience.
• Strong layout knowledge with submicron processes (e.g., 16nm, 7nm, 5nm, 2nm, A14 and below).
• Proficient with Cadence Layout, Cadence Schematic Capture, CALIBRE & Hercules verification tools.
• Experienced in digital (standard cell, memory, I/O) layout; analog layout is a plus.
• Willingness to relocate to Singapore immediately.

Responsibilities

• Understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout.
• Plan schedule timelines and layout floor-planning.
• Deliver high-quality layout and verification within the planned schedule (able to work without supervision for experienced engineers).
• Adapt quickly to new methodologies, openness to new ideas, and effective communication within the library team.

Skills

Memory Layout

Cadence Layout

Cadence Schematic Capture

CALIBRE Verification

Hercules Verification

Floor-planning

Memory Compiler

Script Programming

Team Leadership

Independent Work

Project Management

Layout Topology

Job description

Staff Layout Engineer

Job descriptions and the level of expertise:

Job Description

Staff Layout Engineer

Job descriptions and the level of expertise:

The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.

In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.

Requirements

IC Layout

Strong layout knowledge with a minimum of 8 years of experience

Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.

Strong layout knowledge in submicron processes, e.g. 16nm, 7nm, 5nm,2nm ,A14 and below

Experienced in digital (standard cell, memory, I/O) layout

Experienced in analog layout is also a plus

Job description

IC Layout

Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout

Schedule time-line & layout floor-planning

Complete quality layout and verification within planned schedule (without supervision for experienced engineer)

Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem)

• Strong experience in memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes.
• Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
• Good experience in Floor-planning, hierarchy layout and chip integration.
• Experience in memory compiler will be a plus.
• Knowledge of Script Programming and SKILL Programming would be a plus.
• Able to lead or train a team of junior engineers
• Good knowledge of memory layout topology.
• Ability to lead new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
• Self-reliant, with the ability to work independently as well as in a team.
• Good leadership quality in project management.

Re-location

• Must be available to re-locate to Singapore immediately.

R027299