Senior Layout Engineer: Memory & I/O Cadence Specialist

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED

Singapore

On-site

SGD 70,000 - 110,000

Full time

6 days ago
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Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED is seeking a layout engineer for our Library Group. You will work on memory, I/O, and standard cell layouts, applying stringent rules and process guidelines to ensure quality results.

The role involves floor-planning, scheduling, and delivering complete layouts with verification on time. Experience with Cadence Virtuoso, CALIBRE, and leadership capabilities are essential, with knowledge of advanced submicron nodes highly valued and analog

Qualifications

  • 3–4 years of layout experience in memory/digital I/O
  • Strong layout knowledge across submicron nodes (e.g. 16nm to 1.4nm) and process variations
  • Experience with standard cells, memory, and I/O layouts, with analog layout a plus
  • Proven ability to lead or train junior engineers and work both independently and in a team

Responsibilities

  • Understand and apply layout guidelines for standard cells, I/O memories, and new process rules
  • Plan floor-planning and schedule timelines for layout activities
  • Deliver high-quality layout with verification within planned schedules, with minimal supervision for experienced engineers
  • Adapt to new methodologies and collaborate effectively within the library team

Skills

Memory layout
Team leadership
Independent work
Layout verification
Analog layout (plus)

Tools

Cadence Virtuoso XL/VXL/EXL
CALIBRE
Hercules verification tools
Cadence schematic capture

Job description

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED is seeking a layout engineer for our Library Group. You will work on memory, I/O, and standard cell layouts, applying stringent rules and process guidelines to ensure quality results.

The role involves floor-planning, scheduling, and delivering complete layouts with verification on time. Experience with Cadence Virtuoso, CALIBRE, and leadership capabilities are essential, with knowledge of advanced submicron nodes highly valued and analog

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