Senior Memory & Standard-Cell Layout Engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED is seeking a layout engineer for its Library Group. The role focuses on memory, I/O, and standard cells with strong Cadence tool experience and submicron process knowledge. Lead junior engineers and drive layout methodology improvements.

Responsibilities include strict adherence to layout guidelines, floor-planning, and timely delivery of verified layouts across CMOS processes from 16nm down to 2nm and beyond.

Qualifications

• Minimum 8 years of layout experience.
• Experience in memory, I/O, and standard cell layout.

Responsibilities

• Understand and apply all layout guidelines and rules for quality layout.
• Schedule time-lines and layout floor-planning.
• Deliver high-quality layout and verification with minimal supervision.

Skills

Memory layout design

Physical verifications

LVS

DRC

ERC

Antenna

Electro Migration

Floor-planning

Hierarchy layout

Chip integration

Memory compiler

Script programming

SKILL programming

Team leadership

Technology reviews

Independent work

Tools

Cadence Virtuoso XL/VXL/EXL

CALIBRE verification tools

Job description

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED is seeking a layout engineer for its Library Group. The role focuses on memory, I/O, and standard cells with strong Cadence tool experience and submicron process knowledge. Lead junior engineers and drive layout methodology improvements.

Responsibilities include strict adherence to layout guidelines, floor-planning, and timely delivery of verified layouts across CMOS processes from 16nm down to 2nm and beyond.