Layout Engineer

CURIOUS TEK PTE. LTD.; Singapore; On-site; SGD 90,000 - 120,000; Full time

Job summary

Curious Tek PTE. LTD. in Singapore is seeking an experienced layout engineer to design digital and analog IC layouts, and to support SoC integration with the front-end team. The role requires hands-on expertise in CMOS layouts and strong problem-solving skills to fix DRC/LVS issues.

The ideal candidate holds a bachelor’s degree in Electrical & Electronic Engineering and has 5+ years of layout experience, with proficiency in Cadence, Synopsys, and Mentor Calibre.

Qualifications

• Bachelor’s degree in Electrical & Electronic Engineering or related field with background on IC design (Analog & Digital)
• 5+ years of experience in layout design
• Knowledge of EDA tools (Cadence, Synopsys, Mentor Calibre)
• Knowledge of circuit reliability considerations (ESD, latch-up, aging, EMIR)
• Ability to troubleshoot and rectify layout verification errors on DRC/LVS; familiar with layout signoff flow
• Strong communication, independence, and teamwork

Responsibilities

• Develop digital and analog layout across technologies (e.g., CMOS)
• Layout analog and IO circuits
• Analyse and rectify layout verification issues
• Support front-end team for SoC integration

Skills

Layout design

EDA tools

Troubleshooting

Communication

Education

Bachelor’s degree in Electrical & Electronic Engineering

Tools

Cadence

Synopsys

Mentor Calibre

Job description

Job Responsibilities:

• Develop digital and analog layout in various technologies (e.g., CMOS )
• Layout analog circuits and IO circuits
• Analyse and rectify layout verification issues
• Support the front-end team for System-on-Chip (SoC) integration

Requirements:

• Possess at least a bachelor’s degree or equivalent in Electrical & Electronic Engineering or any related field with background on Integrated Circuit Design (both Analog and Digital)
• 5 years or above experience in the area of layout design.
• Knowledge in Electronic Design Automation (EDA) tools (e.g. Cadence, Synopsys, Mentor Graphic Calibre)
• Knowledge in circuit reliability consideration for layout (e.g., ESD, latch-up, aging, EMIR)
• Able to trouble-shoot and rectify layout verification error on DRC/LVS and familiar with layout signoff flow.
• Strong Communication skills, high level of independence, self-motivation and a good team player.