Layout Engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED is seeking a layout engineer for our Library Group. You will work on memory, I/O, and standard cell layouts, applying stringent rules and process guidelines to ensure quality results.

The role involves floor-planning, scheduling, and delivering complete layouts with verification on time. Experience with Cadence Virtuoso, CALIBRE, and leadership capabilities are essential, with knowledge of advanced submicron nodes highly valued and analog

Qualifications

• 3–4 years of layout experience in memory/digital I/O
• Strong layout knowledge across submicron nodes (e.g. 16nm to 1.4nm) and process variations
• Experience with standard cells, memory, and I/O layouts, with analog layout a plus
• Proven ability to lead or train junior engineers and work both independently and in a team

Responsibilities

• Understand and apply layout guidelines for standard cells, I/O memories, and new process rules
• Plan floor-planning and schedule timelines for layout activities
• Deliver high-quality layout with verification within planned schedules, with minimal supervision for experienced engineers
• Adapt to new methodologies and collaborate effectively within the library team

Skills

Memory layout

Team leadership

Independent work

Layout verification

Analog layout (plus)

Tools

Cadence Virtuoso XL/VXL/EXL

CALIBRE

Hercules verification tools

Cadence schematic capture

Job description

The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.

In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.

Requirements:

• Strong layout knowledge with a minimum of 3 to 4 years of experience
• Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
• Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm , 2nm , 1.4nm etc
• Experienced in digital (standard cell, memory, I/O) layout
• Experienced in analog layout is also a plus

Job Description:

• Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
• Schedule time-line & layout floor-planning
• Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
• Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem):

• Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.
• Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
• Good experience in Floor-planning, hierarchy layout and chip integration.
• Knowledge of Script Programming and SKILL Programming would be a plus.
• Able to lead or train a team of junior engineers
• Good knowledge on memory layout topology.
• Experience in memory compiler will be a plus.
• Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
• Self-reliant, with ability to work independently as well as a team.
• Good leadership quality on project management.