Sr/ DFT Engineer (ASIC / SoC )

Ethos Search Associates Pte Ltd; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

Ethos Search Associates Pte Ltd is seeking a DFT engineer to collaborate with design teams and ensure correct insertion of DFT structures in SoCs.

You will develop, implement and verify DFT schemes on hard-IPs, and test digital logic using ATPG and Scan Compression, while debugging bench/ATE patterns to drive yield improvements.

Qualifications

• BS or MS in Electrical/Electronic/Computer Engineering with at least 1 year of DFT experience.
• Experience implementing chip-level DFT architectures including Scan/Scan Compression.
• Proficiency in Verilog and RTL/GATE/SDF simulation environments.
• Familiarity with MBIST, ATPG and post-silicon debugging is a plus.

Responsibilities

• Collaborate with design teams to ensure DFT structures are correctly inserted.
• Develop and verify DFT schemes on hard-IPs in SoCs.
• Develop techniques to test digital logic using ATPG, Scan Compression, and fault models.
• Debug scan/mbist pattern issues on bench/ATE to identify root causes.
• Assist in Diagnosis and Yield enhancement through the product lifecycle.

Skills

DFT engineering

Verilog

Synthesis & STA

MBIST knowledge

FPGA synthesis

RTL/GATE/SDF

Scripting: Perl/Python/Tcl

Communication skills

Education

Bachelor's or Master's in Electrical/Electronic/Computer Engineering

Tools

DFT tools

ATPG tools

Scan compression tech

Bench/ATE debugging

Job description

Key Responsibilities:

• Work closely with design team and make sure DFT structures are correctly inserted.
• Responsible for developing, implementing and verifying DFT schemes on hard-IPs in SoCs
• Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault model
• Responsible for debugging of scan/mbist pattern issues on bench/ATE to root cause the problem
• Assist in Diagnosis and Yield enhancement through product lifecycle

Qualifications:

• BS or MS in Electrical/Electronic/Computer Engineering with 1 or more experience as DFT engineer
• Experience in creating and implementing complex chip-level DFT architecture
• Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Proficient in logic design using Verilog and experience in synthesis and STA
• Experience in developing test benches and simulation in RTL/GATE/SDF environments
• Knowledge of MBIST is a plus.
• Knowledge of FPGA synthesis and design flow is a plus
• Experience with post-silicon debug and bench setup is a plus
• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, Python etc
• Good communication skills, self-motivated, works well in a group environment that spans across continents