Sr / DFT Engineer ( IP / ASIC / SoC)

AUREXIS TECH PTE. LTD.; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

AUREXIS TECH PTE. LTD. is seeking an engineer to collaborate with design teams to implement DFT structures and verify DFT schemes across ASIC and FPGA IPs.

The role covers block and SoC level ATPG verification with DF T rule checks, and debugging across multiple test modes. The candidate will contribute to MBIST/BISR, IEEE1149.1 JTAG, and IEEE1687 iJTAG testing, while developing firmware-driven test methodologies with built-in diagnostics for efficient debugging on bench and ATE.

Qualifications

• Bachelors degree in Electrical/Electronics/Computer Engineering or equivalent.
• Minimum 1 year of DFT experience and related verification.
• Proficient in Linux environments and scripting (Perl, Tcl, etc.).
• Good communication and teamwork abilities.

Responsibilities

• Work closely with design teams to implement DFT structures.
• Verify DFT schemes on IPs in ASIC and FPGA products.
• Perform block-level and SoC-level ATPG and verification with DFT rule checks and debugging for various test modes.
• Carry out MBIST, BISR, JTAG (IEEE1149.1) and iJTAG testing.
• Develop firmware-driven, cost-effective test methodologies with built-in diagnosis for efficient debugging on bench and ATE.
• Assist in test pattern failure debugging on FPGA-based test environments and ATE throughout the product lifecycle.

Skills

DFT experience

Communication skills

Linux scripting

Education

Electrical/Electronics/Computer Engineering degree

Tools

Tessent SSN

Job description

Main Responsibilities

• Work closely with design teams and make sure DFT structures are correctly implemented
• Responsible for verifying DFT schemes on IPs in ASIC and FPGA products
• Responsible for block level and SoC level ATPG and verification with DFT rule check and debug for various testing modes
• Responsible for memory tests (MBIST, BISR), IEEE1149.1 JTAG and IEEE1687 iJTAG
• Responsible to develop firmware-driven cost-effective test methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench and ATE
• Assist test pattern failure debug and diagnosis on FPGA-based test environment and ATE machine through product lifecycle

Main Requirements

• Degree in Electrical/ Electronics/ Computer Engineering or equivalent with min 1 year DFT experience
• Experience on pre-silicon DFT design specification and scan insertion
• Engineering experience on DFT design verification (ATPG/MBIST/simulation)
• Tessent Streaming Scan Network (SSN) hand-on experience is a big plus
• Post-silicon debug and bench equipment experience
• Good communication skills and team player
• Linux environment and writing /using scripting languages such as Perl, Tcl, etc.