DFT Engineer***

Ethos Search Associates Pte Ltd; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Ethos Search Associates Pte Ltd is seeking a DFT/Testing engineer based in Singapore for a 2-year renewable contract at Changi Business Park. You will drive pre- and post-silicon test solutions and verify DFT schemes across ASIC/FPGA products, including JTAG and iJTAG interfaces.

The role requires hands-on debugging, Linux scripting (Perl/Tcl), and collaboration across continents. Experience with Tessent SSN and EDA tools is a plus, with strong English communication skills essential.

Qualifications

• Pre-silicon DFT design specification and scan insertion experience.
• DFT design verification (ATPG/MBIST) with EDA tools experience.
• Skilled in post-silicon debug and bench equipment.
• Hands-on experience with Tessent Streaming Scan Network (SSN) and FPGA is advantageous.
• Excellent English communication skills
• Able to co-work in a group environment across continents.

Responsibilities

• Drive manufacturing test solutions through pre- and post-silicon activities.
• Ensure DFT structures are correctly implemented and validated.
• Verify DFT schemes on IPS in ASIC and FPGA products.
• Lead block-level and SoC-level ATPG and verification with DFT rule checks.
• Handle memory tests (MBIST, BISR), JTAG/IEEE1149.1 and iJTAG.
• Develop firmware-driven test methodologies with diagnosis for debugging on bench and ATE.
• Troubleshoot test pattern failures on FPGA-based environments and ATE during product life cycle.

Skills

Pre-silicon DFT design

DFT verification (ATPG/MBIST)

Post-silicon debug

Linux scripting (Perl, Tcl)

English communication

Cross-continental collaboration

Tools

Tessent SSN

EDA tools

FPGA

Job description

This will be a 2-years renewable position based in Changi Business Park.

Responsibilities:

• Driving best Manufacturing test solution through pre and post silicon activities
• Ensure DFT structures are correctly implemented
• Verify DFT schemes on Ips in ASIC and FPGA products
• Block level and SoC level ATPG and verification with DFT rule check and debug for various testing modes
• Memory tests (MBIST, BISR), IEEE1149.1 JTAG and IEEE1687 iJTAG
• Develop firmware-driven cost-effective test methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench and ATE
• Test pattern failure debug and diagnosis on FPGA-based test environment and ATE machine through product lifecycle

Requirements:

• Pre-silicon DFT design specification and scan insertion experience.
• DFT design verification (ATPG/MBIST/simulation) with EDA tools experience.
• Skilled in post-silicon debug and bench equipment
• Proficient in Linux environment and writing /using scripting languages such as Perl, Tcl
• Advantageous to have hands-on experience in Tessent Streaming Scan Network (SSN) and FPGA.
• Excellent English communication skills
• Able to co-work in a group environment that spans across continents