Sr/ DFT Engineer (ASIC / SoC )

ETHOS SEARCH ASSOCIATES PTE. LTD.; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

ETHOS SEARCH ASSOCIATES PTE. LTD. invites a knowledgeable DFT engineer to join our semiconductor team in Singapore. You will develop, implement and verify DFT schemes on hard-IPs in SoCs, collaborating with design and verification groups.

Proficiency in Verilog, RTL, and scripting is required, along with hands-on ATPG, scan compression and MBIST. The role covers IP and SoC levels, bench setups, and cross-continental collaboration.

Qualifications

• BS or MS in Electrical/Electronic/Computer Engineering.
• 1+ year of DFT engineer experience.
• Experience creating complex chip-level DFT architectures.
• Experience with Scan Compression, ATPG and MBIST.
• Proficiency in Verilog and RTL design.
• Experience with simulation (RTL/GATE/SDF).
• Linux scripting ability.
• Good communication and teamwork.

Responsibilities

• Work closely with design team and make sure DFT structures are correctly inserted.
• Responsible for developing, implementing and verifying DFT schemes on hard-IPs in SoCs
• Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-At, Transition and Path-Delay fault model
• Responsible for debugging of scan/mbist pattern issues on bench/ATE to root cause the problem
• Assist in Diagnosis and Yield enhancement through product lifecycle

Skills

DFT engineering

Verilog

Synthesis/STA

ATPG

MBIST knowledge

Scripting

Linux

Communication skills

Education

BS or MS in Electrical/Electronic/Computer Engineering

Tools

DFT Tools

ATPG

Scan Compression

Job description

Key Responsibilities:

• Work closely with design team and make sure DFT structures are correctly inserted.
• Responsible for developing, implementing and verifying DFT schemes on hard-IPs in SoCs
• Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault model
• Responsible for debugging of scan/mbist pattern issues on bench/ATE to root cause the problem
• Assist in Diagnosis and Yield enhancement through product lifecycle

Qualifications:

• BS or MS in Electrical/Electronic/Computer Engineering with 1 or more experience as DFT engineer
• Experience in creating and implementing complex chip-level DFT architecture
• Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Proficient in logic design using Verilog and experience in synthesis and STA
• Experience in developing test benches and simulation in RTL/GATE/SDF environments
• Knowledge of MBIST is a plus.
• Knowledge of FPGA synthesis and design flow is a plus
• Experience with post-silicon debug and bench setup is a plus
• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, Python etc
• Good communication skills, self-motivated, works well in a group environment that spans across continents