Backend Engineer – Synthesis/DFT/STA

AMLOGIC SINGAPORE PRIVATE LIMITED; Singapore; On-site; SGD 70,000 - 120,000; Full time

Job summary

AMLOGIC SINGAPORE PRIVATE LIMITED requires a hands-on digital IC engineer to drive synthesis from RTL to gate-level netlists and collaborate across RTL, PnR, and DFT teams. You will help improve PPA for digital modules while ensuring design quality and timing closure.

The role emphasizes DFT duties, including synthesis, scan insertion, ATPG, MBIST, and boundary scan, plus coordination for STA, power, and IR drop analyses in a cross-functional environment.

Qualifications

• Bachelor’s degree in Microelectronics, Electronic Engineering, or a related field.
• Familiarity with backend design flow and EDA tools; DC/FC/TetraMax experience preferred.
• Experience in physical implementation and verification for large-scale chips 28nm or below.
• Proficiency in Verilog, TCL, Perl, and Python is a plus.
• Strong communication, stress management, and teamwork in cross‑departmental settings.

Responsibilities

• Synthesize RTL to gate-level netlist.
• Collaborate with RTL design team to create and verify SDC.
• Work with PnR engineers to improve PPA of digital modules.
• Lead DFT tasks: synthesis, scan insertion, ATPG, MBIST, boundary scan, and functional testing.
• Coordinate with frontend and backend teams for DFT-related STA, power, and IR drop analyses to ensure timing closure.

Skills

Verilog

TCL

Perl

Python

Communication

Teamwork

Stress management

Education

Bachelor’s degree or higher in Microelectronics, Electronic Engineering, or a related field

Tools

DC

FC

TetraMax

Job description

Job Responsibilities

• Responsible for synthesis from RTL to gate-level netlist
• Work with RTL design team to create and verify SDC
• Work with PnR engineers to improve PPA of digital modules
• Responsible for the DFT (Design for Test) tasks of the entire chip or module, including synthesis, scan insertion, ATPG, MBIST, boundary scan, and functional testing.
• Collaborate with front-end and back-end teams to perform DFT-related STA, power, and IR drop analysis, ensuring timing closure for DFT designs.

Qualifications

• Bachelor’s degree or higher in Microelectronics, Electronic Engineering, or a related field.
• Familiarity with backend design flow and tools; experience with EDA tools such as DC/FC/TetraMax is preferred.
• Experience in physical implementation and physical verification for large-scale chips at 28nm or below.
• Proficiency in Verilog, TCL, Perl, and Python is a plus.
• Strong communication, stress management, and teamwork skills, with the ability to work effectively in a cross-departmental environment.