DFT engineer-(Staff/ Senior Staff)

Uni Connect; Singapore; On-site; SGD 120,000 - 190,000; Full time

Job summary

Uni Connect is seeking a senior DFT engineer to insert and optimize scan, boundary scan, and MBIST for an ultra-low power SoC built on subthreshold operation. You will run ATPG, work with EDA tools, and collaborate with designers on timing, power, and physical concerns.

You will also generate test vectors, analyze coverage and test cost, and support pre/post-layout simulations with test engineers to bring up silicon vectors.

Qualifications

• BS/MS in ECE/EE required with 7+ years in DFT.
• Experience in hierarchical DFT architecture for complex SoCs.
• Strong knowledge of timing concepts and constraint development.

Responsibilities

• Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.
• Develop and implement low-power DFT architecture and infrastructure.
• Generate structural test vectors, analyse and improve coverage, test time and test cost.
• Perform pre/post-layout scan and MBIST simulations.
• Work with designers on STA, physical, power and logical issues related to DFT.
• Work with test engineers to bring up test vectors on silicon.

Skills

DFT implementation

Boundary scan

MBIST

ATPG

RTL design

Tcl scripting

English communication

Education

BS in ECE/EE

MS in ECE/EE

Tools

GLS

MBIST simulators

ATP/G tools

Job description

Singapore, Singapore | Posted on 07/25/2025

• Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.
  
• Develop and implement low-power DFT architecture and infrastructure.
  
• Generate structural test vectors, analyse, and improve coverage, test time and test cost.
  
• Perform pre/post-layout scan and MBIST simulations.
  
• Work with designers on STA, physical, power and logical issues related to DFT.
  
• Work with test engineers to bring up test vectors on silicon.
  

Requirements

Specific Experience

• BS/MS in ECE/EE and at least 7 years of experience in DFT implementation.
  
• Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST.
  
• Experience in creating and implementing hierarchical DFT architecture in complex SoC.
  
• Experience in Low-Power DFT and MBIST.
  
• Experience in test time and test coverage analysis for scan and MBIST patterns.
  
• Experience in working with test engineering team to bring up production test program.
  
• Extensive knowledge of timing concepts and constraint development.
  
• Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments.
  
• Experience in RTL is required.
  
• Experience in scripting like Tcl is preferred.
  
• Experience with GLS (gate level simulation) is preferred.
  
• Motivated, self-driven engineer with attention to detail.
  
• Strong verbal and written English communication skills.