Senior Silicon Design Engineer - DFT

advanced micro devices (singapore) pte ltd; Singapore; On-site; SGD 80,000 - 110,000; Full time

Job summary

advanced micro devices (singapore) pte ltd is seeking a design verification engineer to join our team in Singapore. You will drive scan test pattern generation for SERDES IPs and SOCs, troubleshoot pattern and netlist issues with test teams, and work with DFT improvements to enhance product quality.

Applicants should have a strong interest in modern processor architectures, digital design, and verification, with excellent communication and the ability to collaborate across distributed teams.

Qualifications

• Experience with design-for-test methodologies, particularly scan test and automatic test pattern generation.
• Strong knowledge of ATPG tools and their application to pattern generation, fault coverage, and product quality.
• Experience debugging ATPG patterns, scan structures, test models, and gate-level netlists.
• Understanding of IEEE 1149.1 boundary scan, IEEE 1500 embedded core test, and memory built-in self-test concepts.

Responsibilities

• Own the generation, validation, and delivery of scan test patterns for next-generation SERDES IPs and SOCs.
• Partner with product test teams during test bring-up and troubleshoot pattern, model, and netlist issues.
• Improve scan architecture, scan coverage, test models, execution methods, and overall product quality.
• Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
• Collaborate with physical design engineers to support design closure through static timing, clock-domain crossing, netlist, and power analysis.
• Address DFT requirements for high-frequency Phy IP designs while minimizing performance impact.
• Resolve complex interactions between intellectual property and system-on-chip design environments across global teams.
• Develop and implement improvements that simplify design complexity and strengthen engineering quality.

Skills

Communication skills

Analytical thinking

Problem-solving

Willingness to learn

Education

Bachelors or Masters in CE/EE

Tools

Tessent

ATPG tools

IEEE boundary scan tooling

Job description

THE ROLE:

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Own the generation, validation, and delivery of scan test patterns for next-generation SERDES IPs and SOCs.


• Partner with product test teams during test bring-up and troubleshoot pattern, model, and netlist issues.


• Improve scan architecture, scan coverage, test models, execution methods, and overall product quality.


• Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.


• Collaborate with physical design engineers to support design closure through static timing, clock-domain crossing, netlist, and power analysis.


• Address DFT requirements for high-frequency Phy IP designs while minimizing performance impact.


• Resolve complex interactions between intellectual property and system-on-chip design environments across global teams.


• Develop and implement improvements that simplify design complexity and strengthen engineering quality.

PREFERRED EXPERIENCE:

• Experience with design-for-test methodologies, particularly scan test and automatic test pattern generation with Tessent flows.


• Strong working knowledge of industry-standard ATPG tools and their application to pattern generation, fault coverage, and product quality.


• Experience debugging ATPG patterns, scan structures, test models, and gate-level netlists.


• Understanding of IEEE 1149.1 boundary scan, IEEE 1500 embedded core test, and memory built-in self-test concepts.


• Experience with multi-clock and multi-power-domain designs.


• Familiarity with static timing analysis, clock-domain crossing analysis, static power analysis, and physical design closure.


• Experience adapting standard DFT tools or methods to meet the performance requirements of complex, high-frequency designs.


• Demonstrated success collaborating across design, physical design, product engineering, and geographically distributed teams.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering