DFT Engineer*

ETHOS SEARCH ASSOCIATES PTE. LTD.; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

ETHOS SEARCH ASSOCIATES PTE. LTD. in Singapore is seeking a DFT engineer for a 2-year renewable contract based in Changi Business Park. You will drive pre- and post-silicon DFT activities across ASIC/FPGA test flows.

The role requires hands-on DFT verification (ATPG/MBIST), scripting in Linux, and collaboration across continents to implement cost-effective, diagnosable test solutions and efficient debugging on bench and ATE equipment.

Qualifications

• Pre-silicon DFT design specification and scan insertion experience.
• DFT design verification (ATPG/MBIST/simulation) with EDA tools experience.
• Skilled in post-silicon debug and bench equipment.
• Proficient in Linux environment and scripting languages such as Perl, Tcl.
• Advantageous to have hands-on experience in Tessent SSN and FPGA.
• Excellent English communication skills and ability to work with global teams.

Responsibilities

• Drive best Manufacturing test solution through pre and post silicon activities.
• Ensure DFT structures are correctly implemented.
• Verify DFT schemes on Ips in ASIC and FPGA products.
• Block level and SoC level ATPG and verification with DFT rule check and debug for various testing modes.
• Memory tests (MBIST, BISR), IEEE1149.1 JTAG and IEEE1687 iJTAG.
• Develop firmware-driven cost-effective test methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench and ATE.
• Test pattern failure debug and diagnosis on FPGA-based test environment and ATE machine through product lifecycle.

Skills

Pre-silicon DFT design

DFT verification

Linux scripting

Bench equipment handling

Team collaboration

English communication

Tools

Tessent Streaming Scan Network (SSN)

EDA tools

Job description

This will be a 2-years renewable position based in Changi Business Park.

Responsibilities

• Driving best Manufacturing test solution through pre and post silicon activities
• Ensure DFT structures are correctly implemented
• Verify DFT schemes on Ips in ASIC and FPGA products
• Block level and SoC level ATPG and verification with DFT rule check and debug for various testing modes
• Memory tests (MBIST, BISR), IEEE1149.1 JTAG and IEEE1687 iJTAG
• Develop firmware-driven cost-effective test methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench and ATE
• Test pattern failure debug and diagnosis on FPGA-based test environment and ATE machine through product lifecycle

Requirements

• Pre-silicon DFT design specification and scan insertion experience.
• DFT design verification (ATPG/MBIST/simulation) with EDA tools experience.
• Skilled in post-silicon debug and bench equipment
• Proficient in Linux environment and writing /using scripting languages such as Perl, Tcl
• Advantageous to have hands-on experience in Tessent Streaming Scan Network (SSN) and FPGA.
• Excellent English communication skills
• Able to co-work in a group environment that spans across continents