Senior Verification Engineer & Tech Lead – SoC & IP

MediaTek

Singapore

On-site

SGD 70,000 - 110,000

Full time

4 days ago
Be an early applicant

A complete application in a minute

Tailored resume and cover letter, ready to send.

Get past ATS filters

Job summary

MediaTek in Singapore is seeking an experienced verification engineer to develop verification IP, reference models and randomized tests using UVM and SystemVerilog. You will close functional and code coverage while debugging across SystemVerilog, Verilog and SystemC, including low power and formal verification tasks.

The role requires 4–10 years of IC/ASIC verification experience on SOCs and interfaces (Ethernet, PCIe, DDR, USB, ARM CPU) and strong scripting skills.

Qualifications

  • Bachelor’s/Master’s Degree in EEE/Computer/IC design
  • 4-10 years verification experiences
  • IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU
  • Strong experience and debugging ability on SystemVerilog/UVM
  • Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow
  • Experience on Low Power and formal verification is a plus
  • Strong in UNIX scripting with Pyhon, Perl, makefile Cshell
  • Quick to learn new technology
  • Singaporeans and Singapore Permanent Residents are preferred.

Responsibilities

  • Develop verification IP and reference model
  • Implement test with randomization based coverage driven verification methodology
  • Implement functional and functional/code coverage closure
  • Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC: Low Power verification Formal verification

Skills

SystemVerilog
UVM
UNIX scripting
Python
Perl scripting
Makefile
CShell
Low Power verification
Formal verification
ASIC verification
SOC verification
Ethernet
PCIe
DDR
USB
ARM CPU

Education

Bachelor’s/Master’s Degree in EEE/Computer/IC design

Job description

MediaTek in Singapore is seeking an experienced verification engineer to develop verification IP, reference models and randomized tests using UVM and SystemVerilog. You will close functional and code coverage while debugging across SystemVerilog, Verilog and SystemC, including low power and formal verification tasks.

The role requires 4–10 years of IC/ASIC verification experience on SOCs and interfaces (Ethernet, PCIe, DDR, USB, ARM CPU) and strong scripting skills.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Senior/Staff Engineer, Technical Manager (Design Verification)
Senior/Staff Engineer, Technical Manager (Design Verification)

MediaTek • Singapore

On-site
SGD 70,000 - 110,000
Senior SoC Verification Engineer (SystemVerilog/UVM)
Senior SoC Verification Engineer (SystemVerilog/UVM)

Realtek Semiconductor Corp. • Singapore

On-site
SGD 90,000 - 130,000
Semiconductor Design Verification Engineer
Semiconductor Design Verification Engineer

Realtek Semiconductor Corp. • Singapore

On-site
SGD 90,000 - 130,000
Lead engineer-Design verification
Lead engineer-Design verification

Uni Connect • Singapore

On-site
SGD 80,000 - 120,000
Senior ASIC Verification Engineer — SoC & IP Blocks
Senior ASIC Verification Engineer — SoC & IP Blocks

REALTEK SINGAPORE PRIVATE LIMITED • Singapore

On-site
SGD 60,000 - 90,000
Design Verification Engineer II - SoC & Low-Power Wireless
Design Verification Engineer II - SoC & Low-Power Wireless

Silicon Laboratories International Pte Ltd • Singapore

On-site
SGD 120,000 - 180,000
Medical and dental insurance including
Annual health screening
Principal / Senior IC Verification Engineer
Principal / Senior IC Verification Engineer

SEARCH STAFFING SERVICES PTE. LTD. • Singapore

On-site
SGD 110,000 - 170,000
Senior IC Verification Engineer (UVM/SystemVerilog)
Senior IC Verification Engineer (UVM/SystemVerilog)

Ethos Search Associates Pte Ltd • Singapore

On-site
SGD 50,000 - 70,000
SoC Digital Verification Engineer, Multimedia Lab Singapore Regular
SoC Digital Verification Engineer, Multimedia Lab Singapore Regular

ByteDance • Singapore

On-site
SGD 80,000 - 120,000
Design Verification-Staff
Design Verification-Staff

Uni Connect • Singapore

On-site
SGD 90,000 - 150,000