Principal / Senior IC Verification Engineer

Search Staffing Pte Ltd; Singapore; On-site; SGD 110,000 - 170,000; Full time

Job summary

Search Staffing Pte Ltd in Singapore is seeking an experienced Principal / Senior IC Verification Engineer to join our client's growing chip development team. This role focuses on leading functional verification of IPs and SoCs, and contributes to the architecture of reusable testbenches and verification environments.

You will develop verification plans, coverage, and checks, while collaborating closely with design teams.

Qualifications

• Must have proven experience in functional verification of ASICs/SoCs.
• Strong SystemVerilog and UVM proficiency.
• Hands-on with simulators such as VCS, Xcelium, and Questa.
• Proficient in scripting languages: C/C++, Python, Perl, TCL.
• Bonus: formal verification knowledge and FPGA prototyping exposure.

Responsibilities

• Lead functional verification of complex IPs and SoCs.
• Architect and build reusable testbenches and verification environments using UVM.
• Develop verification plans, functional coverage, and assertion checks.
• Debug simulation results and collaborate closely with design teams.
• Automate verification flows and regressions via scripting.
• Support emulation and FPGA prototyping efforts.

Skills

SystemVerilog

UVM

ASIC/SoC verification

C/C++

Python

Perl

TCL

Formal verification

FPGA prototyping

Education

Bachelors/Masters in Electrical/Electronics Eng or CS

Tools

VCS

Xcelium

Questa

Job description

Principal / Senior IC Verification Engineer

Our client, a Singapore-based automotive tech company building AI-powered computing platforms for software-defined vehicles, is looking for an experienced IC Verification Engineer to join their growing chip development team. They specialize in intelligent cockpit systems and autonomous driving computation, combining custom automotive SoCs with advanced software.

What you'll do:

• Lead functional verification of complex IPs and SoCs
• Architect and build reusable testbenches and verification environments using UVM
• Develop verification plans, functional coverage, and assertion checks
• Debug simulation results and collaborate closely with design teams
• Automate verification flows and regressions via scripting
• Support emulation and FPGA prototyping efforts

What you'll bring:

• Bachelor's or Master's in Electrical/Electronics Engineering, Computer Science, or related field
• Solid experience in functional verification of ASICs/SoCs
• Strong SystemVerilog and UVM proficiency
• Hands-on with verification tools/simulators (VCS, Xcelium, Questa)
• Programming/scripting skills (C/C++, Python, Perl, TCL)
• Bonus: formal verification knowledge, emulation/FPGA prototyping exposure