Senior/Staff Engineer, Technical Manager (Design Verification)

MediaTek; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

MediaTek in Singapore is seeking an experienced verification engineer to develop verification IP, reference models and randomized tests using UVM and SystemVerilog. You will close functional and code coverage while debugging across SystemVerilog, Verilog and SystemC, including low power and formal verification tasks.

The role requires 4–10 years of IC/ASIC verification experience on SOCs and interfaces (Ethernet, PCIe, DDR, USB, ARM CPU) and strong scripting skills.

Qualifications

• Bachelor’s/Master’s Degree in EEE/Computer/IC design
• 4-10 years verification experiences
• IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU
• Strong experience and debugging ability on SystemVerilog/UVM
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow
• Experience on Low Power and formal verification is a plus
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell
• Quick to learn new technology
• Singaporeans and Singapore Permanent Residents are preferred.

Responsibilities

• Develop verification IP and reference model
• Implement test with randomization based coverage driven verification methodology
• Implement functional and functional/code coverage closure
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC: Low Power verification Formal verification

Skills

SystemVerilog

UVM

UNIX scripting

Python

Perl scripting

Makefile

CShell

Low Power verification

Formal verification

ASIC verification

SOC verification

Ethernet

PCIe

DDR

USB

ARM CPU

Education

Bachelor’s/Master’s Degree in EEE/Computer/IC design

Job description

• Develop verification IP and reference model
• Implement test with randomization based coverage driven verification methodology
• Implement functional and functional/code coverage closure
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC: Low Power verification Formal verification

What you will bring

• Bachelor's/Master's Degree in EEE/Computer/IC design
• 4-10 years verification experiences
• IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU
• Strong experience and debugging ability on SystemVerilog/UVM
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow
• Experience on Low Power and formal verification is a plus
• Strong in UNIX scripting with Pyhon, Perl, makefile Cshell
• Quick to learn new technology
• Singaporeans and Singapore Permanent Residents are preferred.