Design Verification Engineer II - SoC & Low-Power Wireless

Silicon Laboratories International Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Benefits offered by this job

Medical and dental insurance including

Annual health screening

Job summary

Silicon Labs is seeking an experienced Verificaton Engineer to develop and execute verification plans for wireless IoT SoCs. You will build SystemVerilog/UVM-based testbenches, develop constrained-random test cases, and drive coverage closure across RTL and mixed-signal blocks.

Ideal candidates have 5–10+ years in verification, with strong knowledge of low-power ASIC verification and scripting for automation. This role is on-site at our Singapore office near Tai Seng MRT.

Qualifications

• BS/MS in Electrical or Computer Engineering or equivalent.
• 5–10+ years verification experience.
• Experience in wireless SoC verification preferred.

Responsibilities

• Develop and execute verification plans for SoC/IP blocks and mixed-signal designs.
• Build and maintain SystemVerilog/UVM-based testbenches.
• Create directed and constrained-random test cases.

Skills

SystemVerilog

UVM/OVM

RTL/GLS

Functional coverage

Assertions (SVA)

Python/Perl/TCL

SoC/IP verification

Low-power verification

CDC/RDC verification

AMS verification

Education

BS/MS in Electrical or Computer Engineering

Tools

None

Job description

Silicon Labs is seeking an experienced Verificaton Engineer to develop and execute verification plans for wireless IoT SoCs. You will build SystemVerilog/UVM-based testbenches, develop constrained-random test cases, and drive coverage closure across RTL and mixed-signal blocks.

Ideal candidates have 5–10+ years in verification, with strong knowledge of low-power ASIC verification and scripting for automation. This role is on-site at our Singapore office near Tai Seng MRT.