Senior SoC Verification Engineer (SystemVerilog/UVM)

Realtek Semiconductor Corp.

Singapore

On-site

SGD 90,000 - 130,000

Full time

2 days ago
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Job summary

Realtek Singapore is seeking a seasoned SOC/IP verification engineer to design and execute comprehensive verification plans for complex IP blocks and SoC architectures. The role focuses on building end-to-end verification environments, including stimulus, checkers, assertions, and scoreboards, and integrating with broader DV bring-up efforts.

The ideal candidate will have strong communication and documentation skills, experience with SystemVerilog, UVM, and Python, and the ability to work in a

Qualifications

  • Bachelor or Master in Electronics/Electrical Engineering.
  • Minimum 6+ years of SOC/IP verification experience.
  • Experience with ASIC verification methodologies and flows.

Responsibilities

  • Develop detailed module-level and SoC-level test plans based on design specs.
  • Create ASIC verification environments including stimulus, checkers, assertions, monitors and scoreboards.
  • Develop directed and constraint-random tests and simulate using EDA tools to verify specs.
  • Execute verification plans, bring-up DV, and enable regression for all features.
  • Collaborate with the digital design team to debug test cases and ensure functional designs.

Skills

Strong communication
Analytical
Documentation skills
Interfacing with groups
Independent task handling
Timely delivery

Education

Bachelors/Masters in Electronics/Electrical Engineering

Tools

SystemVerilog
UVM
Python
TCL/Perl

Job description

Realtek Singapore is seeking a seasoned SOC/IP verification engineer to design and execute comprehensive verification plans for complex IP blocks and SoC architectures. The role focuses on building end-to-end verification environments, including stimulus, checkers, assertions, and scoreboards, and integrating with broader DV bring-up efforts.

The ideal candidate will have strong communication and documentation skills, experience with SystemVerilog, UVM, and Python, and the ability to work in a

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