Senior/Staff Process Engineer (Wafer Bumping/Fan-Out)

Lumilens; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Lumilens in Singapore seeks an experienced process development engineer to lead wafer bumping and Fan-Out packaging for silicon photonic chip wafers. You will design early-stage process flows, optimize key steps, and work with OSAT or internal lines to ensure manufacturability.

The role requires 5+ years in wafer bumping or related packaging, hands-on lithography, sputtering, electroplating, and DOE. You will drive reliability tests, root-cause analysis, and documentation for NPI and process

Qualifications

• Bachelor or Master in a technical discipline with 5+ years in wafer bumping or fan-out packaging.
• Hands-on experience with lithography, sputtering, electroplating, and ball drop.
• Familiarity with SEM/CSAM and cross-sectioning for root-cause analysis.
• Strong DOE, reliability testing, and SPC knowledge.
• Experience in OSAT or IDM advanced packaging lines.

Responsibilities

• Lead process development and technical support for wafer bumping and fan-out processes.
• Design and execute DOE to characterize process windows and margins.
• Evaluate materials and qualification of new chemistries.
• Lead reliability validations including TCT, HAST, HTS.
• Manage documentation: SOPs, WI, FMEA, ECOs.

Skills

Wafer bumping

Fan-Out process

Process integration

DOE

Materials characterization

Reliability testing

Failure analysis

SPC

Cross-sectioning

Python

Education

Bachelor's or Master's in Materials Science / Chemical Engineering / Mechanical Engineering

Tools

JMP

Minitab

Python

Job description

• Lead the process development and technical support of the wafer bumping, and/or Fan-Out process for silicon photonic chip wafers, with OSAT or at internal line.
• Process Pathfinding & Integration: Design and optimize early-stage process flows for wafer bumping, thin-film sputtering, lithography, electroplating, and ball drop execution. DOE to characterize process window and margin.
• Material Characterization & Selection: Evaluate and qualify new manufacturing raw materials, including dielectric photoresists, plating chemistries, underfills, and solder alloys.
• Design and execute DOE plans to characterize thermal and mechanical stress. Lead reliability validations including Temperature Cycling Test (TCT), Unbiased Highly Accelerated Stress Test (HAST) and High-Temperature Storage (HTS).
• Failure Analysis & Debug: Own the root-cause diagnostics of structural failure modes unique to WLCSP (e.g., RDL cracking, bridging ball bridging, bump missing, delamination, or wafer warpage). Utilize specialized analytics instrumentation including SEM, CSAM, and physical cross-sectioning. Conduct root cause analysis and formulate improvement solutions.
• Optimize key bumping process parameters including wafer cleaning, UBM sputtering, solder ball plating, reflow and bump inspection to improve bump uniformity and yield.
• Manage incoming wafer quality control, establish SPC control plans and monitor process variation to ensure long‑term process stability
• Compile process SOP, WI, process failure reports and engineering change documents; support NPI new product introduction and process verification.

Core Responsibilities

• Lead the process development and technical support of the wafer bumping, and/or Fan-Out process for silicon photonic chip wafers, with OSAT or at internal line.
• Process Pathfinding & Integration: Design and optimize early-stage process flows for wafer bumping, thin-film sputtering, lithography, electroplating, and ball drop execution. DOE to characterize process window and margin.
• Material Characterization & Selection: Evaluate and qualify new manufacturing raw materials, including dielectric photoresists, plating chemistries, underfills, and solder alloys.
• Design and execute DOE plans to characterize thermal and mechanical stress. Lead reliability validations including Temperature Cycling Test (TCT), Unbiased Highly Accelerated Stress Test (HAST) and High-Temperature Storage (HTS).
• Failure Analysis & Debug: Own the root-cause diagnostics of structural failure modes unique to WLCSP (e.g., RDL cracking, bridging ball bridging, bump missing, delamination, or wafer warpage). Utilize specialized analytics instrumentation including SEM, CSAM, and physical cross-sectioning. Conduct root cause analysis and formulate improvement solutions.
• Optimize key bumping process parameters including wafer cleaning, UBM sputtering, solder ball plating, reflow and bump inspection to improve bump uniformity and yield.
• Manage incoming wafer quality control, establish SPC control plans and monitor process variation to ensure long‑term process stability
• Compile process SOP, WI, process failure reports and engineering change documents; support NPI new product introduction and process verification.

Key Requirements & Qualifications

• Education: A bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline.
• Experience: 5+years of hands‑on wafer bumping or Fan‑out process integration or development experience, at OSAT or IDM internal advanced packaging line. Process exposure/experience on interposer, 2.5D/3D, chip on wafers on substrate, will be an added advantage.
• Technical Knowledge:
• Deep practical understanding and hands‑on experience of photolithography, wet etching, chemical vapor deposition (CVD), and physical vapor deposition (PVD), moulding process adapted for backend bump fabrication.
• Comprehensive command of finite element simulation principles regarding warpage, thermal dissipation, and structural mechanical integrity.
• Solid working expertise with industry validation methodologies including FMEA, SPC controls, and structured 8D problem‑solving tools.
• Software Tools: High proficiency with robust analytical platforms like JMP, Minitab, or Python.