Senior/Staff Process Engineer (Flip Chip)

Lumilens Inc.; Singapore; On-site; SGD 90,000 - 170,000; Full time

Job summary

Lumilens Inc. in Singapore seeks an experienced process engineer to own flip chip process development for silicon photonic wafers. You will lead DOE studies, optimize integration with upstream steps, and drive reliability validations through TCT, HAST and HTS.

Required: 5+ years in flip chip assembly, strong FEM knowledge, and proficiency with JMP or Minitab. Collaboration across teams to ensure yield and manufacturability.

Qualifications

• Education: Bachelor or Master in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or equivalent.
• Experience: 5+ years in flip chip assembly.
• Technical knowledge: plasma cleaning, flux engineering, pick & place, reflow, underfill, curing, and TCB/NCP flux-less flow.
• FEM knowledge: warpage, thermal dissipation, structural integrity.
• Validation: FMEA, SPC, 8D problem-solving.
• Software: JMP and Minitab proficiency.

Responsibilities

• Own the process development and technical support of the Flip Chip process for silicon photonic chip wafers, with OSAT or internal line.
• DOE to characterize process window and margin; optimize integration with upstream processes to increase yield.
• Material characterization and selection for raw materials.
• Design and execute DOE plans to characterize thermal and mechanical stress; lead reliability validations (TCT, HAST, HTS).
• Failure analysis and debugging: root-cause diagnostics and improvements.
• Manage incoming material quality control and SPC control plans.
• Compile SOPs, WIs, failure reports and change documents; support NPI and process verification.

Skills

Process development

DOE planning

Root-cause analysis

Statistical methods

Education

Bachelor/Master in materials science or related engineering

Tools

JMP

Minitab

Job description

Core Responsibilities

1. Owns the process development and technical support of the Flip Chip process for silicon photonic chip wafers, with OSAT or internal line. Process may include plasma cleaning, flux engineering, pick & place, reflow, underfill, curing and/or TCB/NCP flux-less flow.

2. DOE to characterize process window and margin. Optimize process integration with upstream processes (e.g. bump/FO) to increase yield and manufacturability.

3. Material Characterization & Selection: Evaluate and qualify new manufacturing raw materials, including NCP, flux, underfill etc, as applicable.

4. Design and execute DOE plans to characterize thermal and mechanical stress. Lead reliability validations including Temperature Cycling Test (TCT), Unbiased Highly Accelerated Stress Test (HAST) and High-Temperature Storage (HTS).

5. Failure Analysis & Debug: Own the root-cause diagnostics of structural failure modes unique to FC (e.g. flux void, residue, misalignment, die warpage, reflow anomaly, underfill void etc), and formulate improvement solutions.

6. Manage incoming material quality control, establish SPC control plans and monitor process variation to ensure long-term process stability.

7. Compile process SOP, WI, process failure reports and engineering change documents; support NPI new product introduction and process verification.

Key Requirements & Qualifications

• Education: Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline.

• Experience: 5+ years of hands-on industry experience in flip chip assembly.

• Technical Knowledge:

• Deep practical understanding of plasma cleaning, flux engineering, pick & place, reflow, underfill, curing and/or TCB/NCP flux-less flow.

• Comprehensive command of finite element simulation principles regarding warpage, thermal dissipation, and structural mechanical integrity.

• Solid working expertise with industry validation methodologies including FMEA, SPC controls, and structured 8D problem-solving tools.

• Software Tools: High proficiency with robust analytical platforms like JMP, Minitab.