Lead Research Engineer I, Adv Pkg, IME

A*STAR RESEARCH ENTITIES; Singapore; On-site; SGD 150,000 - 210,000; Full time

Job summary

A*STAR RESEARCH ENTITIES is seeking a senior research engineer to lead process integration for high-density multi-chip fan-out wafer level packaging (FOWLP) projects. You will develop new capabilities, design experiments, and optimize lithography, plating and etching steps to meet industry partner requirements.

You will mentor junior colleagues, coordinate with multidisciplinary teams, publish findings in journals and conferences, and contribute to workforce development in semiconductor

Qualifications

• Bachelor's or Master's degree in engineering or sciences.
• 5–10 years in semiconductor device fabrication process integration.
• Hands-on lithography, plating, etching, RDL and bumping experience.
• Knowledge of wafer-level fabrication and advanced packaging tech.
• Strong analytical, data interpretation and design of experiments skills.
• Excellent written and verbal communication.
• Ability to collaborate across OEMs, customers and internal teams.

Responsibilities

• Process integration development for high-density multi-chip FOWLP.
• Develop capabilities for fine pitch RDL, micro bumping, multi-layer RDL.
• Establish novel RDL-first and mold-first FOWLP integration flows.
• Plan short loops with module teams for materials evaluation.
• Collaborate with industry partners to resolve issues and drive quality.
• Lead experiments for process characterization to improve yield.
• Mentor junior colleagues and support capability development
• Publish findings at journals and conferences; contribute to workforce growth

Skills

Analytical skills

Problem-solving

Data analysis

Design of experiments

Communication

Collaboration

Multitasking

Education

Bachelor's/Master's in engineering

Tools

Lithography

Plating

Etching

RDL

Bumping

Wafer-level packaging

Job description

• Process integration development for high density multi-chip fan-out wafer level packaging for various applications such as AI/ HPC, Co-package Optics, Power devices etc.
• Drive the development of new capabilities such as fine pitch RDL, micro bumping, multi-layer RDL, polymer damascene etc required for future FOWLP integration.
• Establish novel RDL-first and mold-first fan-out packaging integration flows to meet industry partners requirements for various applications.
• Plan short loops and work with process module team to develop various processes and materials evaluation for FOWLP.
• Work with industry partners and multidisciplinary team members to execute the projects/assigned tasks by resolving issues.
• Conduct engineering experiments for process characterization to drive quality and yield improvements.
• Coordinate and support engineering build using developed packaging processes and integration.
• Lead industry and internal capability development projects with manageable risks and mentor less experienced colleagues.
• Inspire and mentor young talent in semiconductor technology, contributing to workforce development in the field.
• Publish new findings and technological advancement in prestigious journals and overseas/local conferences.

Job Requirements:

• Bachelors/Masters in Materials Science and Engineering, Mechanical or Chemical Engineering, Electronics, Electrical and Computer Engineering, or any engineering or science related field.
• 5 to 10 years of experience in any semiconductor devices fabrication process integration, and experience in wafer level bumping, RDL and fan-out wafer level package integration will be added advantage.
• Hands‑on experience in semiconductor manufacturing processes such as lithography, plating, etching as well as RDL and bumping process integration.
• Knowledge of wafer level fabrication processes and advanced packaging technologies, methodologies, and reliability characterization is preferable, but not mandatory.
• Strong analytical and problem‑solving skills. Proficiency in data analysis and interpretation and design of experiments.
• Excellent written and verbal communication abilities.
• Ability to work collaboratively in a research-oriented environment (OEMs, customers, and Internal stakeholders). Demonstrated ability to manage multiple tasks and projects simultaneously.
• Demonstrated expertise in heterogeneous integration, FOWLP technologies, and advanced packaging processes.