Senior/Staff Process Engineer (Wafer Dicing & Back-grind)

lumilens; Singapore; On-site; SGD 70,000 - 100,000; Full time

Job summary

lumilens is seeking a skilled process engineer in Singapore focused on the silicon photonics field. The successful candidate will be responsible for the wafer backside grinding/thinning and development processes, ensuring quality and efficiency.

Candidates will need a Bachelor's or Master's in a relevant engineering discipline, alongside at least 3 years of process engineering experience. The company offers a dynamic work environment focused on innovation and quality in advanced packaging.

Qualifications

• 3 to 6+ years of hands-on process engineering experience.
• Familiarity with SPC, JMP data analysis, and DOE matrix design.
• Experience with advanced packaging wafers.

Responsibilities

• Optimize wafer thinning thickness and grinding speed.
• Monitor wafer thickness uniformity and production capacity.
• Compile process SOP, WI, and engineering change documents.

Skills

Process engineering

Wafer thinning

Wafer dicing

Data analysis

Problem-solving

Education

Bachelor or Master degree in Materials Science

Bachelor or Master degree in Chemical Engineering

Bachelor or Master degree in Mechanical Engineering

Bachelor or Master degree in Microelectronics

Job description

Responsibilities

• Responsible for silicon photonic wafer backside grinding/thinning process, laser stealth dicing process and die sorting development for silicon photonic chips, with OSAT or internal line.
• Optimize wafer thinning thickness, grinding speed, cutting path and laser cutting parameters to avoid chip crack, edge chipping and optical structure damage of silicon photonic wafers.
• Solve process abnormalities in wafer thinning and dicing processes, including wafer warpage, surface scratch, incomplete cutting and chip breakage.
• Monitor wafer thickness uniformity, cutting quality and production capacity, carry out continuous process optimization to improve product yield.
• Evaluate process compatibility between wafer grinding/stealth dicing and bumping & flip-chip processes, optimize process integration to avoid subsequent process failure attributed to front-end process variations.
• Compile process SOP, WI, failure reports and engineering change documents; support NPI new product introduction and process verification.

Key Requirements & Qualifications

• Education: A Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline.
• Experience: 3 to 6+ years of hands‑on process engineering in wafer mounting, wafer dicing, wafer thinning or grinding, especially in handling advanced packaging wafers with more complex topology or stack.
• Experience working with external equipment and material suppliers to develop equipment and materials needed to support new assembly requirements. Characterize, qualify and bring the process up for mass production.
• Familiarity with SPC, JMP data analysis, and DOE matrix design for process development and problem identification and solving using meticulous fixing methods.