Senior SoC/ASIC Verification Engineer (RTL, UVM)

HKM HR MANAGEMENT PTE. LTD.; Singapore; On-site; SGD 78,120 - 133,920; Full time

Job summary

A leading company specializing in SoC design and verification is seeking an experienced verification engineer. This role involves working closely with design teams to develop and document extensive test plans, manage verification environments, and mentor junior engineers. Ideal candidates hold a Master's or PhD in Electrical Engineering with substantial experience in verification methodologies and various programming languages. This position promises a dynamic working environment in the semiconductor field.

Qualifications

• Master or PhD in Electrical Engineering with relevant experience.
• Extensive understanding of UVM/OVM and verification methodologies.
• Skilled in multiple programming languages for verification.

Responsibilities

• Develop test plans for SoC design verification.
• Manage automated verification infrastructure.
• Mentor team members to enhance verification processes.

Skills

UVM/OVM

Semiformal Verification

Assertion-based verification

Hardware-software co-verification

Verilog

SystemVerilog

Python

C/C++

Education

Master in Electrical Engineering

PhD in Electrical Engineering

Tools

Perl

TCL

Shell scripting

SystemC

Job description

A leading company specializing in SoC design and verification is seeking an experienced verification engineer. This role involves working closely with design teams to develop and document extensive test plans, manage verification environments, and mentor junior engineers. Ideal candidates hold a Master's or PhD in Electrical Engineering with substantial experience in verification methodologies and various programming languages. This position promises a dynamic working environment in the semiconductor field.