Senior SoC Verification Architect

Uni Connect; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

A leading technology firm in Singapore is seeking a skilled design verification engineer to be responsible for verifying digital and mixed-signal designs. The ideal candidate should have a BSEE/MSEE with 8-12 years of experience in verification, proficiency in SystemVerilog and C/C++, and a strong understanding of low-power battery-operated designs. Key responsibilities include developing test plans, automating test environments, and collaborating with design teams to resolve issues. This position offers opportunities for advanced project involvement in an innovative environment.

Qualifications

• 8-12 years of experience in block, sub-system, and full-chip verification.
• Experience with ARM processor-based designs and low-power techniques is a plus.
• C-based verification in an SoC environment is required.

Responsibilities

• Assume full ownership of DV tasks and deliver high-quality results.
• Develop test plans at block, sub-system, and chip level.
• Automate the test environment for randomized testing.

Skills

Self-starter

Strong understanding of multiple architectures

Proficient in SystemVerilog (UVM)

C/C++ programming

Advanced debugging techniques

Education

BSEE / MSEE

Tools

SystemVerilog

Verilog

C/C++

Python

Job description

A leading technology firm in Singapore is seeking a skilled design verification engineer to be responsible for verifying digital and mixed-signal designs. The ideal candidate should have a BSEE/MSEE with 8-12 years of experience in verification, proficiency in SystemVerilog and C/C++, and a strong understanding of low-power battery-operated designs. Key responsibilities include developing test plans, automating test environments, and collaborating with design teams to resolve issues. This position offers opportunities for advanced project involvement in an innovative environment.