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Job summary
A technology company in Singapore is seeking a Design Verification Manager. You will lead a verification team, develop advanced verification methodologies, and ensure high-quality execution of test plans. The ideal candidate should have strong knowledge of SoC design principles, experience with test plans and EDA tools, and proven leadership skills. A minimum of 10 years in relevant experience is required, with expertise in UVM methodology being essential.
Qualifications
Strong knowledge of SoC design principles, including IP block integration and system-level verification.
Experience with test plan development, execution, and analysis.
Familiarity with EDA tools and development flows for ASIC verification.
Excellent team leader with good communication skills.
Strong expertise in UVM verification methodology.
Experience in C and/or a scripting language such as Python or Perl.
At least 10 years of relevant experience.
Responsibilities
Lead a passionate verification team pushing the limits.
Develop and deploy state-of-the-art verification methodologies.
Conduct thorough test plan reviews and execute on-time.
Achieve zero-defects in the verification process.
Skills
SoC design principles
Test plan development
Communication skills
UVM verification methodology
C programming
Python
Discipline and quality-minded
Leadership
Education
MSEE/BSEE in Electrical Engineering or Computer Engineering
Tools
EDA tools
Job description
A technology company in Singapore is seeking a Design Verification Manager. You will lead a verification team, develop advanced verification methodologies, and ensure high-quality execution of test plans. The ideal candidate should have strong knowledge of SoC design principles, experience with test plans and EDA tools, and proven leadership skills. A minimum of 10 years in relevant experience is required, with expertise in UVM methodology being essential.