Lead RTL Design Engineer for ASIC/SoC

HKM HR MANAGEMENT PTE. LTD.; Singapore; On-site; SGD 80,000 - 110,000; Full time

Job summary

A leading HR management firm in Singapore is seeking an experienced engineer to lead RTL design, simulation, and verification for ASIC/SoC products. Candidates should possess a Master's in Electrical Engineering and a minimum of 5 years of experience in RTL/SoC/digital design. Proficiency in Verilog and SystemVerilog is essential, along with familiarity in collaboration with backend teams. This role provides an exciting opportunity to contribute to cutting-edge technology in a dynamic team environment.

Qualifications

• 5 years of working experience with emphasis on RTL/SoC/digital design.
• Skilled in pre-layout and post-layout simulation.
• Knowledgeable about design flow and collaboration with backend teams.

Responsibilities

• Lead RTL design, simulation, and verification for company ASIC/SoC products.
• Integrate and validate IP blocks for seamless system functionality.
• Analyze requirements for Power, Performance, and Area (PPA).
• Collaborate with backend team in RTL coding, implementation, and synthesis.

Skills

RTL/SoC/digital design

Verilog

SystemVerilog

VCS

Verdi

pre-layout simulation

post-layout simulation

AMBA APB

AXI protocols

RISC/Arm architectures

Education

Master in Electrical Engineering

Tools

VCS

Verdi

Job description

A leading HR management firm in Singapore is seeking an experienced engineer to lead RTL design, simulation, and verification for ASIC/SoC products. Candidates should possess a Master's in Electrical Engineering and a minimum of 5 years of experience in RTL/SoC/digital design. Proficiency in Verilog and SystemVerilog is essential, along with familiarity in collaboration with backend teams. This role provides an exciting opportunity to contribute to cutting-edge technology in a dynamic team environment.