Senior ASIC Verification Engineer (UVM, Formal)

Uni Connect; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

A leading technology firm in Singapore is looking for a design verification engineer. In this role, you will join a dedicated team to develop advanced verification methodologies, aiming for zero defects across complex designs. Applicants should ideally have experience in UVM verification and a relevant degree, with 8 years of experience preferred, though exceptional fresh graduates will also be considered. Knowledge in video processing is a plus, alongside strong programming skills.

Qualifications

• 8 years of relevant experience preferred, but fresh graduates with outstanding results welcome.
• Experience in video processing and video analytics is a plus.
• Disciplined, quality-minded, and driven for excellence.

Responsibilities

• Develop and deploy state-of-the-art verification methodologies.
• Work on complex design verification, from UVM to formal verification.
• Aim for zero-defect in the verification process.

Skills

UVM verification methodology

Team player

Communication skills

General programming

Education

MSEE/BSEE in Electrical Engineering or Computer Engineering

Job description

A leading technology firm in Singapore is looking for a design verification engineer. In this role, you will join a dedicated team to develop advanced verification methodologies, aiming for zero defects across complex designs. Applicants should ideally have experience in UVM verification and a relevant degree, with 8 years of experience preferred, though exceptional fresh graduates will also be considered. Knowledge in video processing is a plus, alongside strong programming skills.