Senior Process Engineer: Ultra-Thin Die Packaging & Scale-Up

STATS ChipPAC; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

STATS ChipPAC is seeking an experienced Senior Process Engineer to drive process development and scale-up for wafer assembly steps such as back grinding, dicing, laser groove, edge trimming, and lamination in our 2.5D/3D packaging lab.

The role focuses on delivering ultra-thin, high-yield, strong diced dies for advanced packaging, with responsibilities spanning process optimization, characterization, and documentation to enable mass production.

Qualifications

• Bachelor or Master in Materials Science, Chemical Engineering, Mechanical Engineering, or Microelectronics.
• 3–6+ years hands-on process engineering in wafer mounting, dicing, thinning or grinding.
• Experience working with external equipment and material suppliers, mass production readiness.
• Familiarity with SPC, JMP data analysis, and DOE matrix design.

Responsibilities

• Develop and optimize wafer backside grinding/thinning, stealth dicing, edge trimming, and lamination processes.
• Characterize process parameters to improve yield and reduce defects in 2.5D/3D packaging.
• Troubleshoot process abnormalities such as warpage, scratches, and incomplete cuts.
• Document SOPs, WI, failure reports, and support ramp-up and process verification.

Skills

Process engineering

Statistical analysis

DOE design

Wafer dicing & thinning

Equipment & supplier liaison

Education

Bachelor or Master in Materials Science or related field

Tools

JMP

SPC software

Job description

STATS ChipPAC is seeking an experienced Senior Process Engineer to drive process development and scale-up for wafer assembly steps such as back grinding, dicing, laser groove, edge trimming, and lamination in our 2.5D/3D packaging lab.

The role focuses on delivering ultra-thin, high-yield, strong diced dies for advanced packaging, with responsibilities spanning process optimization, characterization, and documentation to enable mass production.