Senior Process Engineer

STATS ChipPAC; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

STATS ChipPAC is seeking an experienced Senior Process Engineer to drive process development and scale-up for wafer assembly steps such as back grinding, dicing, laser groove, edge trimming, and lamination in our 2.5D/3D packaging lab.

The role focuses on delivering ultra-thin, high-yield, strong diced dies for advanced packaging, with responsibilities spanning process optimization, characterization, and documentation to enable mass production.

Qualifications

• Bachelor or Master in Materials Science, Chemical Engineering, Mechanical Engineering, or Microelectronics.
• 3–6+ years hands-on process engineering in wafer mounting, dicing, thinning or grinding.
• Experience working with external equipment and material suppliers, mass production readiness.
• Familiarity with SPC, JMP data analysis, and DOE matrix design.

Responsibilities

• Develop and optimize wafer backside grinding/thinning, stealth dicing, edge trimming, and lamination processes.
• Characterize process parameters to improve yield and reduce defects in 2.5D/3D packaging.
• Troubleshoot process abnormalities such as warpage, scratches, and incomplete cuts.
• Document SOPs, WI, failure reports, and support ramp-up and process verification.

Skills

Process engineering

Statistical analysis

DOE design

Wafer dicing & thinning

Equipment & supplier liaison

Education

Bachelor or Master in Materials Science or related field

Tools

JMP

SPC software

Job description

We are seeking an expert Senior Process Engineer to focus on process development, characterization, and mass production scale-up for wafer assembly process steps such as back grinding, dicing, laser groove, edge trimming, lamination etc, in our advanced 2.5D/3D packaging research lab. In this technical role, your primary objective will be developing and delivering ultra-thin, high yield, high strength diced dies for 2.5D/3D advanced packaging.

Key Responsibilities

• Responsible for process development for Si/mold wafer backside grinding/thinning process, laser stealth dicing process, edge trimming process and lamination process for functional chips, with our R&D line.
• Optimize wafer thinning thickness, grinding speed, cutting path and laser cutting parameters to avoid chip crack, and edge chipping for the Si wafers.
• Solve process abnormalities in wafer thinning and dicing processes, including wafer warpage, surface scratch, incomplete cutting and chip breakage.
• Characterize wafer thickness uniformity, cutting quality and production capacity, carry out continuous process optimization to improve product yield.
• New process development for DBG or SDBG process for super thin wafers processing with detailed process characterization.
• Evaluate process compatibility between wafer grinding/stealth dicing and bumping & flip-chip processes, optimize process integration to avoid subsequent process failure attributed to front-end process variations.
• Compile process SOP, WI, failure reports and engineering change documents; support ramp up process setup and process verification.

Key Requirements & Qualification

• Education: A Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline
• Experience: 3 to 6+ years of hands-on process engineering in wafer mounting, wafer dicing, wafer thinning or grinding, especially in handling advanced packaging wafers with more complex topology or stack
• Experience working with external equipment and material suppliers to develop equipment and materials needed to support new assembly requirements. Characterize, qualify and bring the process up for mass production
• Familiarity with SPC, JMP data analysis, and DOE matrix design for process development and problem identification and solving using meticulous fixing methods