Senior IC Layout Engineer - Memory & I/O Lead

Broadcom; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom is seeking a Staff Layout Engineer in Singapore to design memory, I/O, and standard cells. You will lead layout efforts with strong knowledge of submicron processes (16nm/7nm/5nm/2nm and below) and utilization of Cadence tools, CALIBRE and Hercules. Relocation to Singapore is required.

The role emphasizes independent work, teamwork, and potential to mentor junior engineers within the Library Group, part of Central Engineering.

Qualifications

• Minimum 8 years of IC Layout experience.
• Strong layout knowledge with submicron processes (e.g., 16nm, 7nm, 5nm, 2nm, A14 and below).
• Proficient with Cadence Layout, Cadence Schematic Capture, CALIBRE & Hercules verification tools.
• Experienced in digital (standard cell, memory, I/O) layout; analog layout is a plus.
• Willingness to relocate to Singapore immediately.

Responsibilities

• Understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout.
• Plan schedule timelines and layout floor-planning.
• Deliver high-quality layout and verification within the planned schedule (able to work without supervision for experienced engineers).
• Adapt quickly to new methodologies, openness to new ideas, and effective communication within the library team.

Skills

Memory Layout

Cadence Layout

Cadence Schematic Capture

CALIBRE Verification

Hercules Verification

Floor-planning

Memory Compiler

Script Programming

Team Leadership

Independent Work

Project Management

Layout Topology

Job description

Broadcom is seeking a Staff Layout Engineer in Singapore to design memory, I/O, and standard cells. You will lead layout efforts with strong knowledge of submicron processes (16nm/7nm/5nm/2nm and below) and utilization of Cadence tools, CALIBRE and Hercules. Relocation to Singapore is required.

The role emphasizes independent work, teamwork, and potential to mentor junior engineers within the Library Group, part of Central Engineering.