Junior/Senior Circuit Design Engineer (Semiconductor)

talent trader group pte. ltd.; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

talent trader group pte. ltd. is seeking an experienced analog/mixed-signal design engineer in Singapore to contribute to NVM and memory IP development, including design, bring-up and validation.

You will work with layout engineers and support NVM Design Kits, with 3+ years of transistor-level experience and proficiency in Cadence Virtuoso, Spectre, HSPICE, XA and FINESIM.

A Bachelor's or Master's in Microelectronics is required; memory design experience is highly preferred.

Qualifications

• Bachelor's or Master's in Microelectronics or related field.
• 3+ years in transistor-level analog and mixed-signal design.
• Proficient in Cadence Virtuoso, Spectre, HSPICE, XA, FINESIM.
• Experience with CMOS, FinFET, and FD-SOI nodes.
• Memory design experience preferred.
• Understanding of semiconductor processes and layout is a plus.

Responsibilities

• Design and develop semiconductor IPs including NVM, SRAM, ADC/DAC, and high-speed interfaces.
• Provide guidance to layout engineers for NVM memory arrays and analog peripherals.
• Support NVM IP Design Kits with Verilog models, Liberty files, datasheets, bitmaps, and docs.
• Assist design, bring-up, and validation of NVM test chips.
• Ensure project activities meet company quality standards and processes.

Skills

Analog design

Mixed-signal design

Memory design

Cadence Virtuoso

Spectre

HSPICE

XA

FINESIM

CMOS

FinFET

FD-SOI

Layout awareness

Education

Microelectronics degree

Tools

Cadence Virtuoso

Spectre

HSPICE

XA

FINESIM

Job description

Responsibilities

• Participate in the design and development of a wide range of semiconductor IPs, including but not limited to Non-Volatile Memory (NVM), SRAM, ADC/DAC, LDO/DC-DC converters, POR, BOR, Bandgap references, amplifier circuits, PLL/DLL, and high-speed interface IPs.
• Provide technical guidance to layout engineers in the physical implementation of NVM memory arrays and associated analog peripheral circuits.
• Support the development of NVM IP Design Kits (DK), including deliverables such as Verilog models, Liberty files, datasheets, bitmaps, and related documentation.
• Assist with the design, bring-up, and validation of NVM-related test chips.
• Ensure all project activities are executed in accordance with the company's quality standards and processes.

Requirements

• Bachelor's or Master's degree in Microelectronics or a related discipline
• At least 3 years of hands-on experience in transistor-level analog and mixed-signal circuit design.
• Proficient in industry-standard analog EDA tools, including Cadence Virtuoso, Spectre, HSPICE, XA, FINESIM, and similar environments for full-custom design and simulation.
• Experience designing on advanced semiconductor technologies such as CMOS, FinFET, and FD-SOI process nodes.
• Prior experience in memory design is highly preferred.
• Understanding of semiconductor manufacturing processes and physical layout design is considered an advantage.

EA License No: 13C6305

Reg. No.: R1874608 (Lee Jia Hou)