Memory IP Design Engineer for Cutting-Edge Process Tech

Broadcom Singapore Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Benefits offered by this job

Job summary

Broadcom Singapore Pte Ltd is seeking energetic memory design engineers to join the Central Engineering Group and contribute to memory compilers and custom macros on advanced process technology.

You will analyze architectures, design memory blocks, simulate at transistor level, verify layouts, and participate in silicon correlation and test planning with a strong emphasis on reliability and performance.

Qualifications

• Requires a BS in Electrical Engineering and 5+ years of related experience.

Responsibilities

• Analyze different memory architectures and highlight the tradeoffs
• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and leafcell layout integration to build the physical macro
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Specify silicon test plan and correlate silicon to simulation data
• Help debug silicon issues

Skills

Memory compilers

Custom digital circuits

SRAMs

Register files

Multi-ports

ROM

Transistor level behavior

Device physics

Signal integrity

DFT schemes

Chip level integration

Automation scripting

Leadership skills

Education

BS in Electrical Engineering

Tools

Simulators

Job description

Broadcom Singapore Pte Ltd is seeking energetic memory design engineers to join the Central Engineering Group and contribute to memory compilers and custom macros on advanced process technology.

You will analyze architectures, design memory blocks, simulate at transistor level, verify layouts, and participate in silicon correlation and test planning with a strong emphasis on reliability and performance.