Principal/Staff/Senior Engineer, APTD CEM - Advanced Packaging Wafer Level Technology Engineering

WhiteCrow Research; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

WhiteCrow Research is seeking a Principal/Staff/Senior Engineer in Advanced Packaging Wafer Level Technology Engineering. You will develop wafer-level processes, improve yield and cost, and drive quality through data analytics.

Collaboration across packaging, front-end wafer fab, and QA teams is essential for successful product transfers to HVM. The role requires advanced degrees and 2+ years in semiconductor process development, with proficiency in Python, R, SQL, and related tools.

Qualifications

• Bachelor/Master/PhD in a technical discipline related to semiconductor processes.
• Experience in wafer bonding, plating, warpage control, or advanced packaging.
• Strong analytical skills: statistics, DOE, SPC, data dashboards.

Responsibilities

• Develop wafer-level process technologies including thinning and backside interconnect.
• Improve yield, process capability, and manufacturing cost.
• Establish process management projects for future technology nodes.
• Evaluate and implement new equipment and materials.
• Set process parameters for semiconductor manufacturing equipment.
• Drive process quality through inspection, testing, SPC, DOE, and defect analysis.
• Develop advanced process controls using data analytics.
• Collaborate with cross-functional teams across packaging, front-end, and QA.
• Support product transfer from development to high-volume manufacturing.

Skills

Python

R

SQL

Visual Basic

Dashboard development

Education

B.S./M.S./Ph.D. in Chemical Engineering, Electrical/Mechanical Engineering, Physics or related discipline

Tools

E3

FDC

RMS

Job description

We are global talent research, insight, and sourcing specialists with offices in the UK, USA, Singapore, Malaysia, Hong Kong, Dubai, and India. Our international reach has helped us to understand and penetrate specialist markets at a global level. In addition to this, our service is also extended to complement our client’s in-house talent acquisition teams.

About our client

Our client is a global technology leader specializing in advanced memory and storage solutions that power next-generation computing and data-driven applications. With strong expertise in semiconductor innovation, the organization develops high-performance memory technologies across DRAM, NAND, and storage platforms for applications spanning data centers, artificial intelligence, mobile devices, client computing, and intelligent edge ecosystems.

Driven by a commitment to technology advancement, operational excellence, and customer-centric innovation, the company plays a significant role in enabling modern digital infrastructure and compute-intensive workloads worldwide.

As a Principal/Staff/Senior Engineer, APTD CEM - Advanced Packaging Wafer Level Technology Engineering, you will be responsible for...

• Developing wafer-level process technologies including wafer thinning and backside metal interconnect.
• Improving process capability, yield, and manufacturing cost.
• Establishing process management projects supporting future technology nodes.
• Evaluating, qualifying, and implementing new equipment and materials.
• Setting process parameters for semiconductor manufacturing equipment.
• Driving process quality through inspection, testing, measurement, SPC, DOE, and defect analysis.
• Developing advanced process controls using data analytics.
• Collaborating with Package Integration, Assembly Engineering, Front-End Wafer Fab, Product Engineering, Assembly/Test Engineering, and Global Quality teams.
• Supporting product transfer from development through qualification to High Volume Manufacturing (HVM).
• Providing Process of Record (POR) and Model of Record (MOR) documentation.

What you already have...

• B.S./M.S./Ph.D. (or equivalent) in Chemical Engineering, Electrical Engineering, Mechanical Engineering, Physics, or related technical discipline.
• 2+ years of semiconductor process development experience, preferably in wafer bonding, plating, warpage control, or advanced packaging.
• Proficiency in Python, R, and SQL.
• Experience with Visual Basic.
• Knowledge of E3, FDC (Fault Detection & Classification), and RMS (Recipe Management System).
• Strong statistical analysis, process modeling, SPC, DOE, and dashboard development skills.
• Strong understanding of semiconductor process interactions, yield, performance, and reliability.
• Excellent problem-solving and root-cause analysis capability.
• Ability to deliver results under aggressive timelines and limited resources.