Power Integrity (PI) Engineer

Silith Technology; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

Silith Technology is seeking an experienced Power Integrity (PI) Engineer to lead PDN design and PI validation for Co-Packaged Optics (CPO) systems. The role focuses on PDN simulation, silicon capacitor integration, and cross-functional collaboration to deliver stable, high-performance power delivery across advanced architectures.

You will own PI strategies, work with cross-functional teams including IC design, packaging, SI, firmware, and reliability, and drive SI/PI optimization from EVT

Qualifications

• Master's degree or higher in Electrical Engineering, Microelectronics, or related field.
• 5+ years of experience in power integrity or high-speed semiconductor systems.
• Proven experience with PDN design for ASICs, GPUs, AI accelerators, chiplets, or CPO systems.

Responsibilities

• Lead PI design, simulation, validation, and optimization for CPO chiplets and optical engines.
• Architect and optimize end-to-end power delivery across chiplet, package, interposer, RDL, and PCB levels.
• Develop silicon capacitor solutions and models for system-level simulation.
• Collaborate with packaging, IC design, SI, firmware, reliability, foundries and external partners to drive PI innovation.
• Support PI validation during EVT, DVT, and PVT phases.

Skills

Power integrity

PDN design

Silicon capacitors

MIM capacitors

Deep trench capacitors

2.5D/3D packaging

Cross-functional collaboration

PI simulation tools

Education

Master's degree or higher in Electrical Engineering or related field

Tools

Cadence Sigrity

Ansys SIwave/HFSS

Keysight ADS

Job description

About the role

Silith Technology is seeking an experienced Power Integrity (PI) Engineer to join our R&D team in a full-time capacity. The Power Integrity Engineer will lead power delivery and integrity design for CPO systems. This person will own PDN simulation, silicon capacitor applications, and system-level PI validation, while driving strategies to minimize power noise and optimize performance. The PI Engineer partners with cross-functional teams to ensure stable, efficient, and scalable power solutions across complex architectures.

Key responsibilities

• Lead power integrity (PI) design, simulation, validation, and optimization for Co-Packaged Optics (CPO) chiplets, optical engines, and heterogeneous integration systems.

• Architect and optimize end-to-end power delivery solutions across chiplet, package, interposer, RDL, and PCB levels.

• Design and analyze Power Delivery Networks (PDNs), including power rail architecture, power distribution, decoupling strategies, and PI optimization.

• Develop silicon capacitor solutions, including specification, modeling, placement optimization, decoupling network design, and high-frequency noise mitigation.

• Define silicon capacitor requirements such as capacitance density, ESR, ESL, Q-factor, SRF, leakage current, and voltage rating.

• Build and validate capacitor models (S-parameters, SPICE, and equivalent circuit models) for accurate system-level simulation.

• Perform PI and PDN simulations including DC IR drop, AC impedance, resonance, transient response, supply ripple, voltage droop, ground bounce, and power noise analysis.

• Collaborate with packaging, IC design, SI, firmware, reliability teams, foundries, and external partners to drive power delivery innovation and resolve system-level challenges.

• Support PI validation, debugging, and optimization throughout EVT, DVT, and PVT product development phases.

• Develop application, layout, and placement guidelines for advanced silicon capacitor integration in high-speed optical systems.

Key Requirements:

• Master's degree or higher in Electrical Engineering, Microelectronics, Power Electronics, Communications Engineering, or a related field.

• 5+ years of experience in power integrity (PI), high-speed semiconductor systems, package power design, or hardware validation.

• Proven experience with PDN design for ASICs, GPUs, AI accelerators, chiplets, CPO systems, or high-speed SerDes products.

• Strong knowledge of power integrity fundamentals, including PDN/target impedance, decoupling strategies, and resonance analysis.

• Hands-on experience with silicon capacitors, MIM capacitors, deep trench capacitors, and advanced decoupling technologies.

• Solid understanding of high-frequency capacitor behavior, including ESR, ESL, Q-factor, SRF, and parasitic effects.

• Proficiency with PI simulation and analysis tools such as Cadence Sigrity, Ansys SIwave/HFSS, and Keysight ADS.

• Experience with power measurement, characterization, and model extraction using VNAs, impedance analyzers, oscilloscopes, and SPICE modeling.

• Working knowledge of advanced packaging technologies, including 2.5D/3D integration, silicon interposers, RDL, and flip-chip packaging.

• Strong cross-functional collaboration and communication skills, with experience working across IC design, packaging, signal integrity, firmware, and reliability teams.