Power Integrity Engineer for High-Speed Chiplets and CPO

Silith Technology; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

Silith Technology is seeking an experienced Power Integrity (PI) Engineer to lead PDN design and PI validation for Co-Packaged Optics (CPO) systems. The role focuses on PDN simulation, silicon capacitor integration, and cross-functional collaboration to deliver stable, high-performance power delivery across advanced architectures.

You will own PI strategies, work with cross-functional teams including IC design, packaging, SI, firmware, and reliability, and drive SI/PI optimization from EVT

Qualifications

• Master's degree or higher in Electrical Engineering, Microelectronics, or related field.
• 5+ years of experience in power integrity or high-speed semiconductor systems.
• Proven experience with PDN design for ASICs, GPUs, AI accelerators, chiplets, or CPO systems.

Responsibilities

• Lead PI design, simulation, validation, and optimization for CPO chiplets and optical engines.
• Architect and optimize end-to-end power delivery across chiplet, package, interposer, RDL, and PCB levels.
• Develop silicon capacitor solutions and models for system-level simulation.
• Collaborate with packaging, IC design, SI, firmware, reliability, foundries and external partners to drive PI innovation.
• Support PI validation during EVT, DVT, and PVT phases.

Skills

Power integrity

PDN design

Silicon capacitors

MIM capacitors

Deep trench capacitors

2.5D/3D packaging

Cross-functional collaboration

PI simulation tools

Education

Master's degree or higher in Electrical Engineering or related field

Tools

Cadence Sigrity

Ansys SIwave/HFSS

Keysight ADS

Job description

Silith Technology is seeking an experienced Power Integrity (PI) Engineer to lead PDN design and PI validation for Co-Packaged Optics (CPO) systems. The role focuses on PDN simulation, silicon capacitor integration, and cross-functional collaboration to deliver stable, high-performance power delivery across advanced architectures.

You will own PI strategies, work with cross-functional teams including IC design, packaging, SI, firmware, and reliability, and drive SI/PI optimization from EVT