Senior Silicon Photonics Test Engineer (NPI)

Lumilens; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Lumilens is hiring a Senior Silicon Photonics Test Engineer to lead wafer-level test development for Near-Package Optics and Co-Packaged Optics products from NPI to high-volume production. You will own test system architecture, tester design, and integration with die/ASIC components to ensure sustained yield and quality.

You will drive RFQ activities, develop test hardware and software, and mentor production teams on probing and alignment procedures, with close collaboration across manufacturing

Qualifications

• Bachelor’s degree or higher in Electrical Engineering, Optical Engineering, Photonics, Physics, or related field.
• 5+ years of experience in semiconductor or silicon photonics test engineering, with hands-on wafer-level test development experience.
• Proven track record of taking a test platform from NPI through production transfer at volume.
• Experience with wafer-level optical probing/alignment systems (active alignment, fiber array probing) and automated test equipment (ATE).
• Familiarity with high-speed electrical test (SerDes, PAM4/NRZ, BERT) relevant to co-packaged optics electrical interfaces.
• Familiarity with electro-optical measurement instruments (optical power meters, tunable lasers, source meters, network/spectrum analyzers, BERT).
• Working knowledge of DOE, SPC, Gauge R&R, and yield/binning analysis methodologies.
• Understanding of silicon photonics PIC characterization is a plus.
• Understanding of CPO/NPO packaging architecture (die-to-package interconnect, thermal/optical co-design constraints), prior experience with relevant products is a plus.

Responsibilities

• Own and lead the full NPI cycle for silicon photonics wafer level opto-electrical test; design, develop, and qualify wafer-level test systems/testers for NPO/CPO silicon photonics products.
• Own and lead the tester RFQ process; develop test hardware and software and data acquisition for high-speed tests.
• Lead the transfer of wafer-level test platforms from NPI to mass production, ensuring repeatability and reliability at volume.
• Develop and document test process flows, work instructions, and training materials for production operators/technicians.
• Partner with manufacturing, quality, and equipment vendors to qualify wafer-level testers and optical probers on the production floor.
• Provide ongoing engineering support to resolve test-related yield, throughput, or equipment issues in NPO/CPO production.

Skills

Wafer-level test

Si Photonics

ATE

SerDes

PAM4

Optical probing

Data acquisition

DOE

Gauge R&R

Yield analysis

Education

Bachelor's degree

Tools

Wafer probers

Optical fixtures

RF probe cards

BERT/PAM4 hardware

Job description

About LUMILENS

At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing - faster, cooler, and massively more efficient.
We’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry. At Lumilens, we’re developing high-speed photonics products purpose-built to power the future of AI infrastructure and high-performance computing.
This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in scaling optical systems. If you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started.

Job Summary

Senior Silicon Photonics Test Engineer to lead the development of wafer-level test solutions for Near-Package Optics (NPO) and Co-Packaged Optics (CPO) products from the New Product Introduction (NPI) stage through to high-volume production. This role owns the full lifecycle of test development — from architecting wafer-level testers for photonic ICs (PICs) and their integration with switch/ASIC dies, through NPI validation, production transfer, and ongoing engineering support to ensure sustained yield and quality in high-volume manufacturing.

Key Responsibilities

• Own and lead the full NPI cycle for silicon photonics wafer level opto-electrical test; design, develop, and qualify wafer-level test systems/testers for NPO/CPO silicon photonics products.
• Own and lead the tester RFQ process; develop test hardware (wafer probers, optical probe/alignment fixtures, edge/grating coupler interfaces, RF probe cards) and software (automated test sequences, data acquisition, high-speed BERT/PAM4 test integration).
• Lead the transfer of wafer-level test platforms from NPI to mass production, ensuring test repeatability, throughput, optical alignment stability, and reliability targets are met at volume.
• Develop and document test process flows, work instructions, and training materials for production operators/technicians on optical probing and alignment procedures.
• Partner with manufacturing, quality, and equipment vendors to qualify wafer-level testers and optical probers on the production floor.
• Provide ongoing engineering support to resolve test-related yield, throughput, or equipment issues in NPO/CPO production.

Requirements

• Bachelor’s degree or higher in Electrical Engineering, Optical Engineering, Photonics, Physics, or related field.
• 5+ years of experience in semiconductor or silicon photonics test engineering, with hands‑on wafer-level test development experience.
• Proven track record of taking a test platform from NPI through production transfer at volume.
• Experience with wafer-level optical probing/alignment systems (active alignment, fiber array probing) and automated test equipment (ATE).
• Familiarity with high-speed electrical test (SerDes, PAM4/NRZ, BERT) relevant to co-packaged optics electrical interfaces.
• Familiarity with electro‑optical measurement instruments (optical power meters, tunable lasers, source meters, network/spectrum analyzers, BERT).
• Working knowledge of DOE, SPC, Gauge R&R, and yield/binning analysis methodologies.
• Understanding of silicon photonics PIC characterization is a plus.
• Understanding of CPO/NPO packaging architecture (die-to-package interconnect, thermal/optical co-design constraints), prior experience with relevant products is a plus.