Signal Integrity (SI) Engineer

Silith; Singapore; Hybrid; SGD 120,000 - 180,000; Full time

Job summary

Silith in Singapore is seeking a Signal Integrity Engineer to lead high-speed SI design, simulation, and validation for CPO systems. You will optimize SerDes channels, interconnects, and interfaces from chiplet to system level, collaborating across silicon, packaging, and system teams to maximize performance and minimize loss.

You will design, simulate, and test 56G/112G/224G PAM4 links, develop SI models (IBIS, S-parameters), and correlate results with measurements to drive robust high-speed

Qualifications

• Master’s degree or higher in Electronics or a related field.
• 3+ years of experience in signal integrity for high-speed digital systems.
• Deep knowledge of 56G/112G/224G PAM4 SerDes links and high-speed signaling.
• Experience with PCB, packages, interposers, RDLs and connectors.
• Ability to correlate simulation with measurement data.

Responsibilities

• Lead SI design, simulation, analysis, and validation for high-speed paths in optical engines and optoelectronic systems.
• Design and optimize high-speed SerDes channels between ASICs, DSPs, drivers, TIAs, connectors, packages, interposers, and PCBs.
• Perform channel modeling and SI simulation for 112G, 224G PAM4, and next-gen interfaces.
• Analyze insertion loss, return loss, crosstalk, impedance, eye diagrams, jitter, and related SI parameters.
• Develop and maintain SI models (IBIS, IBIS-AMI, S-parameters) and perform channel/system-level SI analysis.
• Correlate simulation results with measurement data and optimize designs.

Skills

Signal integrity

High-speed analysis

Cross-functional collaboration

Test equipment use

Education

Master’s degree or above in Electronics or related field

Tools

Cadence Sigrity

Keysight ADS

Ansys HFSS

Ansys SIwave

Q3D

HyperLynx

Job description

The Signal Integrity Engineer will lead high-speed signal integrity design, simulation, and validation for CPO systems. This role optimizes SerDes channels, interconnects, and high-speed interfaces from chiplet to system level. By collaborating with silicon, packaging, and system teams, the SI Engineer ensures signal paths are designed and validated for maximum performance and minimal loss.

Responsibilities:

• Lead signal integrity design, simulation, analysis, and validation for high-speed signal paths in optical engines and optoelectronic systems.
• Design and optimize high-speed SerDes channels between ASICs, DSPs, drivers, TIAs, connectors, packages, interposers, and PCBs.
• Perform channel modeling and SI simulation for 112G, 224G PAM4, and next-generation high-speed SerDes interfaces.
• Analyze insertion loss, return loss, crosstalk, impedance, reflection, eye diagrams, jitter, and other signal integrity parameters.
• Perform SI simulation and optimization of high-speed interconnect structures, including PCBs, packages, interposers, RDLs, and connectors.
• Develop and maintain high-speed simulation models, including IBIS, IBIS-AMI, and S-parameters, and perform channel-level and system-level SI analysis.
• Correlate simulation results with measurement data, identify signal integrity issues, and develop optimization solutions.
• Define SI design guidelines for high-speed PCB stack-ups, traces, vias, connectors, and related structures.
• Perform high-speed channel testing and validation using VNAs, BERTs, sampling oscilloscopes, and other test equipment.
• Collaborate with hardware, PI, packaging, IC, PCB, and system engineering teams to optimize high-speed CPO products.

Requirements:

• Master’s degree or above in Electronics, Electrical Engineering, Communications, Microelectronics, or a related field.
• 3+ years of experience in signal integrity design for high-speed digital systems, SerDes, optical communications, servers, switches, or related products.
• Strong understanding of 56G/112G/224G PAM4 SerDes links and high-speed differential signaling.
• Solid understanding of the electrical characteristics of high-speed interconnects, including PCBs, packages, interposers, RDLs, and connectors.
• Strong knowledge of SI parameters including insertion loss, return loss, crosstalk, impedance, eye diagrams, and jitter.
• Proficiency in one or more SI simulation tools such as Cadence Sigrity, Keysight ADS, Ansys HFSS, Ansys SIwave, Q3D, and HyperLynx.
• Solid understanding of IBIS, IBIS-AMI, S-parameters, and channel simulation methodologies.
• Hands-on experience with VNAs, BERTs, sampling oscilloscopes, and other high-speed test equipment, with the ability to correlate simulation and measurement results.
• Experience with CPO, 800G/1.6T optical modules, 224G SerDes, ASIC packages, or high-speed interposer development is preferred.
• Strong high-speed signal analysis, simulation, troubleshooting, and cross-functional communication skills.

Tools you will master and utilize daily: