Senior Power Integrity Engineer for ASIC/SoC Signoff

ByteDance; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

ByteDance in Singapore is seeking a Power Integrity engineer for ASIC/SoC development. You will own PI signoff across the full design flow, collaborate with front-end and physical teams, and drive PI methodologies for new process nodes and power architectures.

The role emphasizes deep PI analysis, EM/IR drop expertise, and cross-functional problem solving. Ideal candidates have 5+ years in PI for ASIC/SoC, hands-on experience with leading PI tools, and a BS in Electrical Engineering.

Qualifications

• BS degree in Electrical Engineering or equivalent practical experience.
• 5+ years of power integrity analysis experience for ASIC/SoC designs.
• Hands-on experience with PI tools (RedHawk-SC, PT-PX, Voltus).
• Experience with static and dynamic IR drop analysis, EM analysis, and power grid analysis.
• PI signoff flow from early design through tapeout.

Responsibilities

• Own PI signoff for advanced-node ASIC/SoC designs including PI signoff for power delivery networks.
• Lead full-chip and block-level PI analysis from design to tapeout.
• Drive PI methodology bring-up for new process nodes and PDKs.
• Analyze and debug PI results: IR hotspots, EM violations, power-grid issues, and decap effectiveness.
• Collaborate with PD, RTL, Power, Package, Foundry, and EDA teams to resolve PI issues.
• Interface with Foundry and EDA vendors on PI rules, tool correlation, and model validation.
• Develop and optimize PI methodologies for vector-based and vectorless analysis and load-step analysis.
• Establish PI signoff criteria and provide guidance to peers.

Skills

Power integrity

PI tools

ASIC/SoC experience

EM analysis

Education

BS in Electrical Engineering

Tools

Ansys RedHawk-SC

Synopsys PT-PX

Cadence Voltus

Job description

ByteDance in Singapore is seeking a Power Integrity engineer for ASIC/SoC development. You will own PI signoff across the full design flow, collaborate with front-end and physical teams, and drive PI methodologies for new process nodes and power architectures.

The role emphasizes deep PI analysis, EM/IR drop expertise, and cross-functional problem solving. Ideal candidates have 5+ years in PI for ASIC/SoC, hands-on experience with leading PI tools, and a BS in Electrical Engineering.