Power Integrity (PI) Engineer

Silith; Singapore; Hybrid; SGD 120,000 - 180,000; Full time

Job summary

Silith seeks a Power Integrity Engineer to lead power delivery and integrity design for complex CPO systems. You will own PDN simulation, silicon capacitor applications, and system-level PI validation, collaborating with IC, package, SI, and reliability teams to minimize power noise and optimize performance.

You will develop PDN architectures, validate high-frequency capacitor models, and use Cadence Sigrity, Ansys SIwave/HFSS, and Keysight ADS to analyze PDN stability across chiplet,

Qualifications

• Master’s degree or above in Electrical Engineering, Microelectronics, Power Electronics, Communications Engineering, or related fields.
• 5+ years of experience in power integrity, high-speed semiconductor systems, package power design, or system-level hardware validation.
• Experience with PDN design for ASICs, GPUs, AI accelerators, CPO systems, chiplets, or high-speed SerDes products.
• Strong understanding of power integrity concepts, including decoupling networks.
• Experience with silicon capacitors, MIM capacitors, deep trench capacitors, or advanced packaging capacitor technologies.

Responsibilities

• Own power integrity design, simulation, and validation for CPO chiplets, optical engines, and high-speed heterogeneous integration systems.
• Develop power delivery architectures for CPO systems, including PDN planning and optimization for various devices.
• Design chiplet- and package-level PDN, including power integrity optimization.
• Develop silicon capacitor applications and models for high-frequency power delivery.
• Perform PDN simulations covering DC IR drop, PDN resonance, and supply ripple.
• Collaborate with IC design, package, SI, firmware, and reliability teams to solve system-level power challenges.

Skills

Power integrity

PDN design

System-level hardware validation

Cross-functional collaboration

Education

Master’s degree in Electrical Engineering or related field

Tools

Cadence Sigrity

Ansys SIwave

Ansys HFSS

Keysight ADS

VNA

Job description

The Power Integrity Engineer will lead power delivery and integrity design for CPO systems. This person will own PDN simulation, silicon capacitor applications, and system-level PI validation, while driving strategies to minimize power noise and optimize performance. The PI Engineer partners with cross-functional teams to ensure stable, efficient, and scalable power solutions across complex architectures.

Responsibilities:

• Own power integrity (PI) design, simulation, and validation for CPO chiplets, optical engines, and high-speed heterogeneous integration systems.
• Develop power delivery architectures for CPO systems, including power distribution planning and optimization for PICs, TIAs, drivers, AFEs, MCUs, ASICs, and other integrated devices.
• Design chiplet-level and package-level PDN (Power Delivery Network), including:
• Power integrity optimization.
• Develop silicon capacitor applications for CPO chiplets, including:
• Capacitor selection;
• High-frequency power noise optimization.
• ESR;
• ESL;
• Q Factor;
• Self-Resonant Frequency (SRF);
• Leakage Current;
• Voltage Rating.
• Develop and validate high-frequency silicon capacitor models, including:
• S-parameters;
• Equivalent circuit models.
• Perform PDN simulations including:DC IR drop;
• PDN resonance;
• Supply ripple.
• Analyze and optimize power delivery issues including:
• Dynamic current response.
• Design power delivery solutions across chiplet, package, interposer, RDL, and PCB levels.
• Collaborate with advanced packaging engineers to optimize:
• Interposer power routing;
• RDL power distribution;
• Work with foundry partners to define silicon capacitor requirements, including:
• Device structure requirements;
• Electrical performance targets;
• Application requirements.
• Layout guidelines;
• Support PI validation, debugging, and optimization during EVT, DVT, and PVT phases.
• Collaborate with IC design, package, SI, firmware, and reliability teams to solve system-level power challenges.

Requirements:

Master’s degree or above in Electrical Engineering, Microelectronics, Power Electronics, Communications Engineering, or related fields.

5+ years of experience in power integrity, high-speed semiconductor systems, package power design, or system-level hardware validation.

Experience with PDN design for ASICs, GPUs, AI accelerators, CPO systems, chiplets, or high-speed SerDes products.

Strong understanding of power integrity concepts, including:

Decoupling networks;

Experience with silicon capacitors, MIM capacitors, deep trench capacitors, or advanced packaging capacitor technologies.

Understanding of high-frequency capacitor characteristics, including:

ESR;

ESL;

Q factor;

SRF;

Parasitic effects.

Experience with PI simulation tools:

Cadence Sigrity;

Ansys SIwave;

Ansys HFSS;

Keysight ADS.

Experience with power measurement and model extraction methods, including:

VNA;

Impedance analyzer;

Knowledge of advanced packaging technologies:

2.5D/3D packaging;

RDL;

Strong collaboration skills with IC design, package, SI, firmware, and reliability teams.

Tools you will master and utilize daily: