IC Design Engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED is seeking an R&D engineer for design and physical implementation of high-performance System-On-Chip ASICs.

The role requires leading teams in physical design of large ASICs, and using top EDA tools to implement 5nm/3nm/2nm processes. Qualifications include a PhD/Master's in Electrical/Electronics/Computer Engineering and hands-on scripting (Perl, Tcl, Python) with strong problem-solving.

Qualifications

• Degree, Masters or PhD in Electrical/Electronics/Computer engineering with 7 years or more experience in a relevant field.
• Familiarity with one or more VLSI design tools (Cadence, Synopsys, Mentor & Ansys) for Place & Route, Spice Simulation, DRC/LVS Physical Verification, Static Timing Analysis and Power Integrity
• Strong analytical problem-solving skills and the ability to collaborate in cross-functional team environments
• Experience in Perl, Tcl & Python Scripting languages

Responsibilities

• Lead the design and implementation of 500–800 million gate ASICs in 5nm/3nm/2nm processes using commercial and in-house EDA tools.
• Collaborate with RTL and Physical Design teams to resolve timing violations through design or constraint optimization.
• Provide technical support to customers and manage customer relationships during project execution.

Skills

Team leadership

Customer relationship management

EDA tool proficiency

CPU/DSP architecture knowledge

Timing optimization collaboration

Scripting (Perl Tcl Python)

Education

Master's or PhD in Electrical/Electronics/Computer Engineering

Tools

Cadence

Synopsys

Mentor

Ansys

Job description

1. R&D engineer position available in design and physical implementation of high-performance System-On-Chip ASICs. Key competencies required are:

• Working experience leading team in physical design implementation of large ASICs (500 to 800 million gates complexity).
• Demonstrated ability in providing technical support to customers and managing customer working relationship.
• Demonstrated strong technical hands-on competency in using leading edge physical design EDA tools in projects.
• In-depth CPU/DSP architecture/algorithm working knowledge and related physical design implementation knowledge highly advantageous.
• Collaborating with RTL and Physical Design teams to resolve timing violations through design or constraint optimization.

2. Utilize commercial and in-house EDA tools for the design and implementation of 500 ~ 800 million gate integrated circuits in 5nm/3nm/2nm process technologies.

3. Opportunity to participate in innovation, design flow and methodology development to address challenges of designing into deep submicron processes and state-of-the-art ASIC design for computing and networking products

Qualifications: Requirements

1. Degree, Masters or PhD in Electrical/Electronics/Computer engineering with 7 years or more experience in a relevant field.

2. Familiarity with one or more VLSI design tools (Cadence, Synopsys, Mentor & Ansys) for Place & Route, Spice Simulation, DRC/LVS Physical Verification, Static Timing Analysis and Power Integrity

3. Strong analytical problem-solving skills and the ability to collaborate in cross-functional team environments

4. Experience in Perl, Tcl & Python Scripting languages