Memory Design Automation - Memory Modeling

PERSOL SINGAPORE PTE. LTD.; Singapore; On-site; SGD 90,000 - 180,000; Full time

Job summary

PERSOL SINGAPORE PTE. LTD. is looking for a memory front-end engineer to lead the development of memory design kits, RTL models, and ATPG for the ASIC flow. You will optimize automation using Perl or Python and validate models with Synopsys and Mentor Graphics EDA tools.

Apply your Verilog expertise to ensure functional memory circuit correctness, collaborate with memory design and compiler teams, and support RTL, verification, and DFT groups to deliver robust front-end solutions.

Qualifications

• Bachelor’s degree or higher in Electrical/Electronics engineering or related field.
• Knowledge of high-performance SRAM/ROM and VLSI design is a plus.
• Proficiency in Perl, Shell, Python, C/C++ and AI/ML basics is advantageous.
• Solid understanding of Verilog (behavioral, RTL, synthesizable) required.
• Familiarity with Liberty timing syntax is a plus.
• Experience with EDA tools (VCS, QuestaSim, NC) required.
• DFT: Tessent, Fastscan; Synthesis: Design Compiler, Genus; Simulation: VCS, QuestaSim, NC; STA: PrimeTime.
• Strong scripting and flow automation skills; good team collaboration.

Responsibilities

• Lead development and coding of front-end design kits, memory RTL and ATPG models.
• Create and optimize automation flows using Perl or Python to improve efficiency.
• Use EDA tools from Synopsys and Mentor Graphics to validate models.
• Stay updated on modeling standards and tool vendor advancements.
• Ensure functional correctness of memory circuits against models.
• Collaborate with memory design and compiler teams to deliver front-end kits.
• Troubleshoot model issues with RTL designers, verification teams, DFT, and tool vendors.

Skills

Perl

Python

C/C++

Verilog

Team player

Scripting

Education

Bachelor’s Degree or higher in Electrical Engineering or Electronics Engineering

Tools

VCS

QuestaSim

NC

Design Compiler

Genus

PrimeTime

Tessent

Fastscan

Job description

Job Description

• Lead the development and coding of front-end design kits, including memory RTL models, ATPG models, and other views essential for ASIC design flow.

• Create and optimize automation flows and scripts using Perl or Python to enhance workflow efficiency and ensure model accuracy.

• Utilize EDA tools from vendors such as Synopsys and Mentor Graphics to validate model correctness.

• Maintain up-to-date knowledge of current modeling standards and advancements from EDA tool vendors to enhance memory IP performance and meet the latest ASIC design flow requirements.

• Ensure the functional correctness of memory circuits by validating them against memory models.

• Collaborate with the memory design team and compiler development team to deliver comprehensive memory front-end design kits.

• Troubleshoot and resolve model issues in collaboration with RTL designers, design verification teams, DFT teams, and tool vendors.

Job Requirements

• Bachelor’s Degree or higher in Electrical Engineering, Electronics Engineering, or related discipline.

• Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage. Experience with EDA tools will be helpful.

• Proficient with Perl, Shell, Python, C/C++ languages, knowledge with AI machine learning algorithm and infrastructure is an added advantage.

• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.

• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.

• Understanding of liberty timing syntax is a plus.

• Knowledge and experience with EDA simulation tools such as VCS, NC is required.

• Experience with EDA tools will be helpful:

• DFT: Logicvision, Tessent, Fastscan

• Synthesis: Design compiler, Genus

• Simulation tools:VCS, QuestaSim, NC

• STA tools such as PrimeTime

• Good scripting and flow automation skills, in Perl or Python.

• A team player, meticulous, able to work and learn independently are important attributes for this job.