Memory Modeling & Automation Intern - Front-End ASIC Design

MediaTek; Singapore; On-site; SGD 60,000 - 100,000; Full time

Job summary

MediaTek engineers are seeking a memory modelling specialist to lead front-end kit development, RTL modeling, and ATPG model creation. You will craft automation using Perl or Python and validate models with industry-standard EDA tools to ensure robust memory IP performance within the ASIC flow.

The role emphasizes collaboration with memory design and compiler teams, plus problem-solving with RTL, DFT, and tool vendors to keep modeling standards current.

Qualifications

• Foundational knowledge of front-end design flow including RTL development.
• Experience with EDA tools (DFT, synthesis, simulation) is beneficial.
• Strong scripting in Perl or Python and good team skills.

Responsibilities

• Lead the development and coding of front-end design kits, including memory RTL models, ATPG models, and other views essential for ASIC design flow.
• Create and optimize automation flows and scripts using Perl or Python to enhance workflow efficiency and ensure model accuracy.
• Utilize EDA tools from vendors such as Synopsys and Mentor Graphics to validate model correctness.
• Maintain up-to-date knowledge of modeling standards and advancements from EDA tool vendors to enhance memory IP performance.
• Ensure the functional correctness of memory circuits by validating them against memory models.
• Collaborate with the memory design team and compiler development team to deliver memory front-end design kits.
• Troubleshoot and resolve model issues in collaboration with RTL designers, design verification teams, DFT teams, and tool vendors.

Skills

Digital design concepts

RTL development

Perl/Python scripting

Team player

Troubleshooting

Tools

Logicvision

Tessent

Fastscan

Design Compiler

Genus

VCS

QuestaSim

PrimeTime

Job description

MediaTek engineers are seeking a memory modelling specialist to lead front-end kit development, RTL modeling, and ATPG model creation. You will craft automation using Perl or Python and validate models with industry-standard EDA tools to ensure robust memory IP performance within the ASIC flow.

The role emphasizes collaboration with memory design and compiler teams, plus problem-solving with RTL, DFT, and tool vendors to keep modeling standards current.