AI ASIC Memory Compiler Engineer

MediaTek; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

MediaTek in Singapore is seeking a memory design automation engineer to collaborate with global teams on high-performance memory design. The role includes developing behavioral models and debugging SRAM models for ASIC design.

The ideal candidate will have proficiency in programming languages like Perl, Shell, Python, and C/C++. Experience with EDA tools and a good understanding of design flows is crucial for success in this position.

Qualifications

• Knowledge of high performance, low power SRAM/ROM design is an added advantage.
• Experience with EDA simulation tools such as VCS, NC is required.
• Good understanding of Verilog syntax (behavioral, RTL, synthesizable) is essential.

Responsibilities

• Develop behavioral, FPGA, timing and DFT simulation models for memory design.
• Debug and optimize SRAM models for ASIC design flow.
• Work collaboratively with worldwide memory design teams.

Skills

Perl

Shell

Python

C/C++

VLSI design

Tools

EDA tools

VCS

QuestaSim

PrimeTime

Job description

Job Description

At Mediatek’s Memory Design Automation team, we work seamlessly with worldwide memory design teams to deliver high performance, low power and small area in‑house memories design kits and design flows under advanced technology nodes. We are looking for a candidate to join us as a memory design automation engineer for the delivery of robust memory and development of Memory Compiler automation flow. The role will be required to develop behavioral, FPGA, timing and DFT simulation models and debug/optimize SRAM models for ASIC design flow.

Main Requirements and Qualifications

• Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage. Experience with EDA tools will be helpful.
• Proficient with Perl, Shell, Python, C/C++ languages, knowledge with AI machine learning algorithm and infrastructure is an added advantage.
• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.
• Good understanding of liberty timing syntax.
• Knowledge and experience with EDA simulation tools such as VCS, NC is required.
• Experience with EDA tools will be helpful:
  • DFT: Logicvision, Tessent, Fastscan
  • Synthesis: Design compiler, Genus
  • Simulation tools: VCS, QuestaSim, NC
  • STA tools such as PrimeTime