AI ASIC Memory Compiler Engineer

MediaTek Research Lab Inc.; Singapore; On-site; SGD 60,000 - 80,000; Full time

Job summary

MediaTek Research Lab Inc. is seeking a Memory Design Automation Engineer to develop robust memory solutions and automation flows. The role involves creating simulation models and optimizing SRAM models for ASIC design.

Candidates should possess knowledge of high performance SRAM/ROM design and be proficient in programming languages like Python, C/C++, and Perl. Experience with EDA tools like VCS and NC is required.

Qualifications

• Experience with high performance, low power SRAM/ROM and VLSI design is an added advantage.
• Knowledge of behavioral, RTL and synthesizable Verilog is required.
• Experience with EDA tools is helpful.

Responsibilities

• Develop behavioral, FPGA, timing and DFT simulation models.
• Debug and optimize SRAM models for ASIC design flow.

Skills

Knowledge of SRAM/ROM and VLSI design

Proficient with Perl

Proficient with Shell

Proficient with Python

Proficient with C/C++

Understanding of AI machine learning algorithms

Good understanding of Verilog syntax

Understanding of liberty timing syntax

Experience with EDA simulation tools

Tools

EDA tools

VCS

NC

Job description

At Mediatek’s Memory Design Automation team, we work seamlessly with worldwide memory design teams to deliver high performance, low power and small area in-house memories design kits and design flows under advanced technology nodes. We are looking for candidate to join us as memory design automation engineer for the delivery of robust memory and development of Memory Compiler automation flow. The role will be required to develop behavioral, FPGA, timing and DFT simulation models and debug/optimize SRAM models for ASIC design flow.

Main Requirements and Qualifications

• 1. Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage. Experience with EDA tools will be helpful.
• 2. Proficient with Perl, Shell, Python, C/C++ languages, knowledge with AI machine learning algorithm and infrastructure is an added advantage.
• 3. Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.
• 4. Good understanding of liberty timing syntax.
• 5. Knowledge and experience with EDA simulation tools such as VCS, NC is required
• 6. Experience with EDA tools will be helpful: